coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/intel/meteorlake: Disable 3-strike error
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74159 to look at the new patch set (#3). Change subject: soc/intel/meteorlake: Disable 3-strike error ...................................................................... soc/intel/meteorlake: Disable 3-strike error This patch calls into API to disable 3-strike error on Meteor Lake SoC based platform. TEST=Able to build and boot google/rex to ChromeOS. Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled ``` localhost ~ # iotools rdmsr 0 0x1a4 0x0000000000000900 ``` Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74159/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 Gerrit-Change-Number: 74159 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set Power Performance Platform Override
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74155 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Set Power Performance Platform Override ...................................................................... soc/intel/meteorlake: Set Power Performance Platform Override According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set. This patch is backported from `commit 117770d32468e63df ("soc/intel/ alderlake: Enable Energy/Performance Bias control")`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 21 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 62639a1..691f50d 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -72,10 +72,11 @@ msr.hi = 0; wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); - /* Enable PROCHOT */ + /* Enable PROCHOT and Power Performance Platform Override */ msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ msr.lo |= (1 << 23); /* Lock it */ + msr.lo |= (1 << 18); /* Power Performance Platform Override */ wrmsr(MSR_POWER_CTL, msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8 Gerrit-Change-Number: 74155 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add EPP override support
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74154 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Add EPP override support ...................................................................... soc/intel/meteorlake: Add EPP override support This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. This patch is backported from `commit 0bb2225718ef898c ("soc/intel/alderlake: Add EPP override support")`. BUG=b:266522659 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/cpu.c 2 files changed, 47 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 9bafb22..9d9a600 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -346,6 +346,10 @@ /* Enable PCH to CPU energy report feature. */ bool pch_pm_energy_report_enable; + + /* Energy-Performance Preference (HWP feature) */ + bool enable_energy_perf_pref; + uint8_t energy_perf_pref_value; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 31b7ef2..62639a1 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -124,6 +124,12 @@ /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); + const config_t *conf = config_of_soc(); + /* Set energy-performance preference */ + if (conf->enable_energy_perf_pref) + if (check_energy_perf_cap()) + set_energy_perf_pref(conf->energy_perf_pref_value); + /* Enable Turbo */ enable_turbo(); @@ -140,6 +146,19 @@ smm_relocate(); } +static void pre_mp_init(void) +{ + soc_fsp_load(); + + const config_t *conf = config_of_soc(); + if (conf->enable_energy_perf_pref) { + if (check_energy_perf_cap()) + enable_energy_perf_pref(); + else + printk(BIOS_WARNING, "Energy Performance Preference not supported!\n"); + } +} + static void post_mp_init(void) { /* Set Max Ratio */ @@ -160,7 +179,7 @@ * that are set prior to ramstage. * Real MTRRs programming are being done after resource allocation. */ - .pre_mp_init = soc_fsp_load, + .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, -- To view, visit https://review.coreboot.org/c/coreboot/+/74154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326 Gerrit-Change-Number: 74154 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: commonlib/coreboot_tables.h: Fix typo in enum type name
by Benjamin Doron (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Maximilian Brune, Angel Pons, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74120 ) Change subject: commonlib/coreboot_tables.h: Fix typo in enum type name ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74120/comment/78570d28_bffc02c8 PS1, Line 9: Fix a typo in an enum's type name, "tmp" ---> "tpm". The enum type is > kind of raises the questions why we have it, if its not used. […] It's an enum, we can use it unnamed. These could be defines, but I don't think it matters? Or, we can just remove the type name too. -- To view, visit https://review.coreboot.org/c/coreboot/+/74120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7529e7ee80aa9661ec053da8211c2c3295b3942 Gerrit-Change-Number: 74120 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 07:15:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib/coreboot_tables.h: Replace spaces with tabs
by Lean Sheng Tan (Code Review) 02 Apr '23

02 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74119 ) Change subject: commonlib/coreboot_tables.h: Replace spaces with tabs ...................................................................... commonlib/coreboot_tables.h: Replace spaces with tabs Indent with tabs for the sake of consistency with the rest of the code. Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74119 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/commonlib/include/commonlib/coreboot_tables.h 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Benjamin Doron: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index e299e54..1e83577 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -85,7 +85,7 @@ LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, LB_TAG_TYPE_C_INFO = 0x0042, - LB_TAG_ACPI_RSDP = 0x0043, + LB_TAG_ACPI_RSDP = 0x0043, LB_TAG_PCIE = 0x0044, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, -- To view, visit https://review.coreboot.org/c/coreboot/+/74119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233 Gerrit-Change-Number: 74119 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
by Lean Sheng Tan (Code Review) 02 Apr '23

02 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74116 ) Change subject: soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP ...................................................................... soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/google/brya/variants/aurash/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/moli/overridetree.cb M src/mainboard/google/brya/variants/zydron/overridetree.cb M src/mainboard/starlabs/starbook/variants/adl/devtree.c M src/mainboard/system76/adl/variants/darp8/overridetree.cb M src/mainboard/system76/adl/variants/galp6/overridetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb 10 files changed, 37 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Sean Rhodes: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index e407094..bd3e9d1 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -50,7 +50,7 @@ .tdp_pl1_override = 15, .tdp_pl2_override = 25, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 64, }" device domain 0 on diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index faed00d..a6b1a08 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -87,7 +87,7 @@ register "tcc_offset" = "10" # TCC of 90 - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 30, .tdp_pl2_override = 60, .tdp_pl4 = 90, diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 97682bd..8b06732 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -83,7 +83,7 @@ }, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 43, .tdp_pl4 = 105, diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index ded70f2..cad69bb 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -51,7 +51,7 @@ register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 55, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 64, }" device domain 0 on diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb index ed3595b..49d8302 100644 --- a/src/mainboard/google/brya/variants/zydron/overridetree.cb +++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb @@ -83,7 +83,7 @@ }, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 43, .tdp_pl4 = 105, diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c index 0b764fd..27ab6c9 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c @@ -16,7 +16,7 @@ common_config = chip_get_common_soc_structure(); struct soc_power_limits_config *soc_conf_10core = - &cfg->power_limits_config[ADL_P_282_482_28W_CORE]; + &cfg->power_limits_config[ADL_P_282_442_482_28W_CORE]; struct soc_power_limits_config *soc_conf_12core = &cfg->power_limits_config[ADL_P_682_28W_CORE]; diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 5f82c44..a4dbed8 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # HACK: Limit PL4 to PL2 to prevent power-off when system is booted on # battery power. This seems to only happen with the i7 units. - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56, .tdp_pl4 = 56, // FIXME: Set to 65 diff --git a/src/mainboard/system76/adl/variants/galp6/overridetree.cb b/src/mainboard/system76/adl/variants/galp6/overridetree.cb index c10e17a..cac4df6 100644 --- a/src/mainboard/system76/adl/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl/variants/galp6/overridetree.cb @@ -1,5 +1,5 @@ chip soc/intel/alderlake - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 60, .tdp_pl4 = 90, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 04a4a22..b6fc43d 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -42,7 +42,7 @@ /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { ADL_P_142_242_282_15W_CORE, - ADL_P_282_482_28W_CORE, + ADL_P_282_442_482_28W_CORE, ADL_P_682_28W_CORE, ADL_P_442_482_45W_CORE, ADL_P_642_682_45W_CORE, @@ -102,13 +102,14 @@ { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W }, + { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_442_482_28W_CORE, TDP_28W }, + { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_442_482_28W_CORE, TDP_28W }, { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W }, { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W }, { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_282_442_482_28W_CORE, TDP_28W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 2b9d380..b9abe06 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -8,7 +8,7 @@ .tdp_pl4 = 123, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 90, -- To view, visit https://review.coreboot.org/c/coreboot/+/74116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Gerrit-Change-Number: 74116 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
by Maximilian Brune (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tim Crawford, Tarun Tuli, Patrick Rudolph, Subrata Banik, Jeremy Soller. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74116 ) Change subject: soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Gerrit-Change-Number: 74116 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 03:59:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib/coreboot_tables.h: Fix typo in enum type name
by Maximilian Brune (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Angel Pons, Lean Sheng Tan. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74120 ) Change subject: commonlib/coreboot_tables.h: Fix typo in enum type name ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74120/comment/98c756e0_8be6bf99 PS1, Line 9: Fix a typo in an enum's type name, "tmp" ---> "tpm". The enum type is kind of raises the questions why we have it, if its not used. Think it would be okay to just remove it? -- To view, visit https://review.coreboot.org/c/coreboot/+/74120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7529e7ee80aa9661ec053da8211c2c3295b3942 Gerrit-Change-Number: 74120 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 03:57:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib/coreboot_tables.h: Replace spaces with tabs
by Maximilian Brune (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Angel Pons, Lean Sheng Tan. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74119 ) Change subject: commonlib/coreboot_tables.h: Replace spaces with tabs ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233 Gerrit-Change-Number: 74119 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 03:55:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2
by Felix Singer (Code Review) 02 Apr '23

02 Apr '23

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73791 ) Change subject: crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Mention in the 4.20 release notes. -- To view, visit https://review.coreboot.org/c/coreboot/+/73791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62078257fd84a64c699a7f930bc306e38d2f4058 Gerrit-Change-Number: 73791 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Apr 2023 02:29:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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