coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2
by Elyes Haouas (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Felix Singer, Jason Glenesk, Martin L Roth, Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73791 ) Change subject: crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73791/comment/b729c480_db57717b PS3, Line 8: > CMake 3.26. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62078257fd84a64c699a7f930bc306e38d2f4058 Gerrit-Change-Number: 73791 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Apr 2023 15:41:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set Power Performance Platform Override
by build bot (Jenkins) (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74155 ) Change subject: soc/intel/meteorlake: Set Power Performance Platform Override ...................................................................... Patch Set 6: Verified+1 (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172884): https://review.coreboot.org/c/coreboot/+/74155/comment/07b25cf6_deec1c35 PS6, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172884): https://review.coreboot.org/c/coreboot/+/74155/comment/86c6c2cd_b90c7c05 PS6, Line 11: This patch is backported from Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 117770d32468 ("soc/intel/alderlake: Enable Energy/Performance Bias control")' -- To view, visit https://review.coreboot.org/c/coreboot/+/74155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8 Gerrit-Change-Number: 74155 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 01 Apr 2023 15:30:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set AES-NI Lock
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Ronak Kanabar, Eric Lai. Hello Tarun Tuli, Kapil Porwal, Ivy Jian, Ronak Kanabar, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74160 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Set AES-NI Lock ...................................................................... soc/intel/meteorlake: Set AES-NI Lock This function performs locking of the AES-NI enablement state. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74160/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Gerrit-Change-Number: 74160 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: isoc/intel/meteorlake: Perform feature control lock
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74162 ) Change subject: isoc/intel/meteorlake: Perform feature control lock ...................................................................... isoc/intel/meteorlake: Perform feature control lock This function calls into `set_feature_ctrl_lock()` to lock IA32_FEATURE_CONTROL MSRfeature control. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42 --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74162/1 diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index da2b51a..9c03a86 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -147,6 +147,9 @@ /* Enable Vmx */ set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx); + + /* Feature control lock configure */ + set_feature_ctrl_lock(); } static void per_cpu_smm_trigger(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/74162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42 Gerrit-Change-Number: 74162 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74161 ) Change subject: soc/intel/meteorlake: Enable VMX ...................................................................... soc/intel/meteorlake: Enable VMX This function calls into `set_feature_ctrl_vmx_arg()` to enable VMX for virtualization. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/cpu.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74161/1 diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 9d9a600..d4abed8 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -350,6 +350,8 @@ /* Energy-Performance Preference (HWP feature) */ bool enable_energy_perf_pref; uint8_t energy_perf_pref_value; + + bool disable_vmx; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 6d017bd..da2b51a 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -144,6 +144,9 @@ if (CONFIG(INTEL_TME) && is_tme_supported()) set_tme_core_activate(); + + /* Enable Vmx */ + set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx); } static void per_cpu_smm_trigger(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: isoc/intel/meteorlake: Set AES-NI Lock
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74160 ) Change subject: isoc/intel/meteorlake: Set AES-NI Lock ...................................................................... isoc/intel/meteorlake: Set AES-NI Lock This function performs locking of the AES-NI enablement state. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74160/1 diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 50ff3b2..6d017bd 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -120,6 +120,8 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); + set_aesni_lock(); + enable_pm_timer_emulation(); /* Enable Direct Cache Access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Gerrit-Change-Number: 74160 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Disable 3-strike error
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74159 ) Change subject: soc/intel/meteorlake: Disable 3-strike error ...................................................................... soc/intel/meteorlake: Disable 3-strike error This patch calls into API to disable 3-strike error on Meteor Lake SoC based platform. TEST=Able to build and boot google/rex to ChromeOS. Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled ``` localhost ~ # iotools rdmsr 0 0x1a4 0x0000000000000900 ``` Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74159/1 diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 691f50d..50ff3b2 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -104,6 +104,9 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* Disable 3-strike error */ + disable_three_strike_error(); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears -- To view, visit https://review.coreboot.org/c/coreboot/+/74159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 Gerrit-Change-Number: 74159 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error ...................................................................... soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error This patch prevents the Three Strike Counter from incrementing, which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74158/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index bfa4818..3f0ee67 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -569,3 +569,12 @@ { return cpu_get_max_turbo_ratio() * CONFIG_CPU_BCLK_MHZ; } + +void disable_three_strike_error(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PREFETCH_CTL); + msr.lo = msr.lo | DISABLE_CPU_ERROR; + wrmsr(MSR_PREFETCH_CTL, msr); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index c72e1ea..a33a722 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -222,4 +222,11 @@ * Returns true if Key Locker feature is supported otherwise false. */ bool is_keylocker_supported(void); + +/* + * This function prevents the Three Strike Counter from incrementing, + * it will help to collect more useful CPU traces for debugging. + */ +void disable_three_strike_error(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index d4d8732..9f95e9f 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -35,6 +35,7 @@ #define MSR_PREFETCH_CTL 0x1a4 #define PREFETCH_L1_DISABLE (1 << 0) #define PREFETCH_L2_DISABLE (1 << 2) +#define DISABLE_CPU_ERROR (1 << 11) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MISC_PWR_MGMT_ISST_EN (1 << 6) -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex: Add FW_CONFIG for FP/UWB/WIFI
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74146 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex: Add FW_CONFIG for FP/UWB/WIFI ...................................................................... mb/google/rex: Add FW_CONFIG for FP/UWB/WIFI This patch adds FW_CONFIG to accommodate different Rex BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent 2. Ultra wideband - UWB Absent/Using BITBANG/Using GSPI1 3. WIFI - CNVi/PCIe TEST=Able to build and boot google/rex. Change-Id: I97b0dc25f239103a0a235f14b50008a633e2f88d Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74146 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index ff4f647..44d20cb 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -28,6 +28,19 @@ option USB4_ANX7452 3 option USB4_HAYDEN_BRIDGE 4 end + field FP 15 + option FP_PRESENT 0 + option FP_ABSENT 1 + end + field UWB 16 17 + option UWB_ABSENT 0 + option UWB_BITBANG 1 + option UWB_GSPI1 2 + end + field WIFI 18 + option WIFI_CNVI 0 + option WIFI_PCIE 1 + end end chip soc/intel/meteorlake -- To view, visit https://review.coreboot.org/c/coreboot/+/74146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97b0dc25f239103a0a235f14b50008a633e2f88d Gerrit-Change-Number: 74146 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/rex: Update Rex Flash Layout
by Subrata Banik (Code Review) 01 Apr '23

01 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66288 ) ( 17 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex: Update Rex Flash Layout ...................................................................... mb/google/rex: Update Rex Flash Layout This patch updates the Rex flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. For default chromeos.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:262868089 TEST=Able to enable CSE update on google/rex and have free space to add one more PUNIT FW for support different SoC stepping. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66288 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/chromeos-debug-fsp.fmd M src/mainboard/google/rex/chromeos.fmd 2 files changed, 67 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/chromeos-debug-fsp.fmd b/src/mainboard/google/rex/chromeos-debug-fsp.fmd index e57b4dd..bd250f5f 100644 --- a/src/mainboard/google/rex/chromeos-debug-fsp.fmd +++ b/src/mainboard/google/rex/chromeos-debug-fsp.fmd @@ -4,39 +4,33 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7M { - VBLOCK_A 64K + RW_SECTION_A 7604K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K + ME_RW_A(CBFS) 4400K } - RW_MISC 1M { + RW_MISC 152K { + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. - # It is placed in the common `chromeos.fmd` file because it is only 4K and there - # is free space in the RW_MISC region that cannot be easily reclaimed because - # the RW_SECTION_B must start on the 16M boundary. - RW_SPD_CACHE(PRESERVE) 4K - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 64K + RW_SECTION_B 7604K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K + ME_RW_B(CBFS) 4400K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/rex/chromeos.fmd b/src/mainboard/google/rex/chromeos.fmd index 1714e80..3521232 100644 --- a/src/mainboard/google/rex/chromeos.fmd +++ b/src/mainboard/google/rex/chromeos.fmd @@ -4,41 +4,35 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 6M { - VBLOCK_A 64K + RW_SECTION_A 7092K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K + ME_RW_A(CBFS) 4400K } - RW_LEGACY(CBFS) 2M - RW_MISC 1M { + RW_MISC 152K { + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. - # It is placed in the common `chromeos.fmd` file because it is only 4K and there - # is free space in the RW_MISC region that cannot be easily reclaimed because - # the RW_SECTION_B must start on the 16M boundary. - RW_SPD_CACHE(PRESERVE) 4K - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 6M { - VBLOCK_B 64K + RW_SECTION_B 7092K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K + ME_RW_B(CBFS) 4400K } + RW_LEGACY(CBFS) 1M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 8M { -- To view, visit https://review.coreboot.org/c/coreboot/+/66288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78 Gerrit-Change-Number: 66288 Gerrit-PatchSet: 19 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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