coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error
by Paul Menzel (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai, Lean Sheng Tan, Ronak Kanabar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error ...................................................................... Patch Set 3: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/cbe1a0e4_09348fd0 PS3, Line 7: API to disable 3-strike Machine Check CAT error Please make it a statement by adding a verb (in imperative mood). Also it’s just one function, so maybe: > Add function to … https://review.coreboot.org/c/coreboot/+/74158/comment/6a6d27ad_a13a362b PS3, Line 8: Please describe the problem, including what CAT means, and maybe a reference to the documentation of that counter. https://review.coreboot.org/c/coreboot/+/74158/comment/cda0abfb_435f113d PS3, Line 10: would help helps https://review.coreboot.org/c/coreboot/+/74158/comment/5307a652_3d6ed963 PS3, Line 9: This patch prevents the Three Strike Counter from incrementing, : which would help to disable Machine Check Catastrophic error. : It will provide more opportunity to collect more useful CPU : traces for debugging. Please use the fully allowed text width of 72 characters per line. File src/soc/intel/common/block/include/intelblocks/cpulib.h: https://review.coreboot.org/c/coreboot/+/74158/comment/9adac654_aef33709 PS3, Line 227: , . https://review.coreboot.org/c/coreboot/+/74158/comment/ab1a71d7_4258d791 PS3, Line 228: it will help It helps -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 13:42:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Order the CPUs based on their APIC IDs
by 9elements QA (Code Review) 02 Apr '23

02 Apr '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72131 ) Change subject: soc/intel/common: Order the CPUs based on their APIC IDs ...................................................................... Patch Set 12: Automatic boot test returned (PASS/FAIL/TOTAL): 7 / 1 / 8 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/157275 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/157274 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/157273 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/157272 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/157271 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/157270 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/157269 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/157268 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/72131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Gerrit-Change-Number: 72131 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 11:54:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Order the CPUs based on their APIC IDs
by Sridhar Siricilla (Code Review) 02 Apr '23

02 Apr '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72131 ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/common: Order the CPUs based on their APIC IDs ...................................................................... soc/intel/common: Order the CPUs based on their APIC IDs The patch defines acpi_set_cpu_apicid_order() which orders the APIC IDs based on APIC IDs of Performance cores and Efficient cores, calculates the total core count and total Performance cores count, populates the information in the cpu_apicid_order_info struct. The helper function useful to present the Performance and Efficient cores in order to OS through MADT table and _CPC object. TEST=Verify the build for Gimble (Alder Lake board) Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 86 insertions(+), 57 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 81c4add..a6f9103 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -1,12 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <intelblocks/acpi.h> -#include <soc/cpu.h> -#include <smp/spinlock.h> -#include <device/device.h> -#include <device/path.h> +#include <bootstate.h> +#include <commonlib/sort.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> +#include <cpu/cpu.h> +#include <device/path.h> +#include <intelblocks/acpi.h> +#include <soc/cpu.h> +#include <types.h> #define CPPC_NOM_FREQ_IDX 22 #define CPPC_NOM_PERF_IDX 3 @@ -16,12 +19,62 @@ CPU_TYPE_PERF, }; -DECLARE_SPIN_LOCK(cpu_lock); -static u8 global_cpu_type[CONFIG_MAX_CPUS]; +struct cpu_apic_info_type { + /* + * Ordered APIC IDs based on core type. + * Array begins with Performance Cores' APIC IDs, + * then followed by Efficeint Cores's APIC IDs. + */ + int32_t apic_ids[CONFIG_MAX_CPUS]; -static bool is_perf_core(void) + /* Total CPU count */ + uint8_t total_cpu_cnt; + + /* + * Total Performance core count. This will be used + * to identify the start of Efficient Cores's + * APIC ID list + */ + uint8_t perf_cpu_cnt; +}; + +static struct cpu_apic_info_type cpu_apic_info; + +/* + * The function orders APIC IDs such that orders first Performance cores and then + * Efficient cores' APIC IDs in ascending order. Also calculates total number of + * Performance cores and all cores count in the system and populates the information + * in the cpu_apic_info sturct. + */ +static void acpi_set_hybrid_cpu_apicid_order(void *unused) { - return get_soc_cpu_type() == CPUID_CORE_TYPE_INTEL_CORE; + size_t perf_core_cnt = 0, eff_core_cnt = 0; + int32_t eff_apic_ids[CONFIG_MAX_CPUS] = {0}; + extern struct cpu_info cpu_infos[]; + uint32_t i, j = 0; + + for (i = 0; i < ARRAY_SIZE(cpu_apic_info.apic_ids); i++) { + if (cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF) + cpu_apic_info.apic_ids[perf_core_cnt++] = + cpu_infos[i].cpu->path.apic.apic_id; + else + eff_apic_ids[eff_core_cnt++] = + cpu_infos[i].cpu->path.apic.apic_id; + } + + if (perf_core_cnt > 1) + bubblesort(cpu_apic_info.apic_ids, perf_core_cnt, NUM_ASCENDING); + + for (i = perf_core_cnt; j < eff_core_cnt; i++, j++) + cpu_apic_info.apic_ids[i] = eff_apic_ids[j]; + + if (eff_core_cnt > 1) + bubblesort(&cpu_apic_info.apic_ids[perf_core_cnt], eff_core_cnt, NUM_ASCENDING); + + /* Populate total core count */ + cpu_apic_info.total_cpu_cnt = perf_core_cnt + eff_core_cnt; + + cpu_apic_info.perf_cpu_cnt = perf_core_cnt; } static enum cpu_perf_eff_type get_core_type(void) @@ -36,52 +89,6 @@ info->cpu->path.apic.core_type = get_core_type(); } -static struct device *get_cpu_bus_first_child(void) -{ - struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); - assert(dev != NULL); - return (dev->link_list)->children; -} - -static u32 get_cpu_index(void) -{ - u32 cpu_index = 0; - struct device *dev; - u32 my_apic_id = lapicid(); - - for (dev = get_cpu_bus_first_child(); dev; dev = dev->sibling) - if (my_apic_id > dev->path.apic.apic_id) - cpu_index++; - - return cpu_index; -} - -/* - * This function determines the type (performance or efficient) of the CPU that - * is executing it and stores the information (in a thread-safe manner) in an - * global_cpu_type array. - * It requires the SoC to implement a function `get_soc_cpu_type()` which will be - * called in a critical section to determine the type of the executing CPU. - */ -static void set_cpu_type(void *unused) -{ - spin_lock(&cpu_lock); - u8 cpu_index = get_cpu_index(); - - if (is_perf_core()) - global_cpu_type[cpu_index] = CPU_TYPE_PERF; - - spin_unlock(&cpu_lock); -} - -static void run_set_cpu_type(void *unused) -{ - if (mp_run_on_all_cpus(set_cpu_type, NULL) != CB_SUCCESS) { - printk(BIOS_ERR, "cpu_hybrid: Failed to set global_cpu_type with CPU type info\n"); - return; - } -} - static void acpi_get_cpu_nomi_perf(u16 *eff_core_nom_perf, u16 *perf_core_nom_perf) { u8 max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); @@ -114,7 +121,7 @@ acpi_get_cpu_nomi_perf(&eff_core_nom_perf, &perf_core_nom_perf); - if (global_cpu_type[core_id] == CPU_TYPE_PERF) + if (core_id < cpu_apic_info.perf_cpu_cnt) acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, perf_core_nom_perf); else acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, @@ -144,4 +151,4 @@ acpigen_pop_len(); } -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, run_set_cpu_type, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, acpi_set_hybrid_cpu_apicid_order, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/72131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Gerrit-Change-Number: 72131 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/common: Order the CPUs based on their APIC IDs
by Sridhar Siricilla (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Sukumar Ghorai, Elyes Haouas. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72131 ) Change subject: soc/intel/common: Order the CPUs based on their APIC IDs ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72131/comment/a57a137f_8ce5855a PS11, Line 16: Verify the build for Gimble (Alder Lake board) > It is tested on Rex as well, but Test details are not updated . […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Gerrit-Change-Number: 72131 Gerrit-PatchSet: 11 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 02 Apr 2023 10:53:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74168 ) Change subject: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Patchset: PS1: We need to wait until we dropped CpuFeaturesPei.ffs module inside ChromeOS FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/74168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Gerrit-Change-Number: 74168 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 10:44:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74168 ) Change subject: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS ...................................................................... soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS The Intel FSP used on ChromeOS platform has dropped the `CpuFeaturesPei.ffs` module to opt for coreboot running those additional feature programming on BSP and APs. TEST=Able to build and boot google/rex without any boot regression. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/74168/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 3d99f81..c34f255 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -366,7 +366,7 @@ config DROP_CPU_FEATURE_PROGRAM_IN_FSP bool - default y if MP_SERVICES_PPI_V2_NOOP + default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS default n help This is to avoid FSP running basic CPU feature programming on BSP -- To view, visit https://review.coreboot.org/c/coreboot/+/74168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Gerrit-Change-Number: 74168 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Option to drop redundant CPU feature programming
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74167 ) Change subject: soc/intel/meteorlake: Option to drop redundant CPU feature programming ...................................................................... soc/intel/meteorlake: Option to drop redundant CPU feature programming This patch introduces a new config named `DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU feature programming on BSP and on APs using the "CpuFeaturesPei.efi" module. Most of these featureprogramming are getting performed today in scope of coreboot doing MP Init. Running these redundant programming in scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) would results in CPU exception. SoC users to select this config after dropping "CpuFeaturesPei.ffs" module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional feature programming on BSP and APs. This feature is default enabled, in case of "coreboot running MP init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/74167/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index b29b3bc..3d99f81 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -364,4 +364,25 @@ help Set this option if debug build of FSP is used. +config DROP_CPU_FEATURE_PROGRAM_IN_FSP + bool + default y if MP_SERVICES_PPI_V2_NOOP + default n + help + This is to avoid FSP running basic CPU feature programming on BSP + and on APs using the "CpuFeaturesPei.efi" module. The feature programming + includes enabling x2APIC, MCA, MCE and Turbo etc. + + Most of these feature programming are getting performed today in scope + of coreboot doing MP Init. Running these redundant programming in scope + of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) would + results in CPU exception. + + SoC users to select this config after dropping "CpuFeaturesPei.ffs" module + from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional + feature programming on BSP and APs. + + This feature is default enabled, in case of "coreboot running MP init" + aka MP_SERVICES_PPI_V2_NOOP config is selected. + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Gerrit-Change-Number: 74167 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Perform feature control lock
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74162 to look at the new patch set (#3). Change subject: soc/intel/meteorlake: Perform feature control lock ...................................................................... soc/intel/meteorlake: Perform feature control lock This function calls into `set_feature_ctrl_lock()` to lock IA32_FEATURE_CONTROL MSRfeature control. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42 --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74162/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42 Gerrit-Change-Number: 74162 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74161 to look at the new patch set (#3). Change subject: soc/intel/meteorlake: Enable VMX ...................................................................... soc/intel/meteorlake: Enable VMX This function calls into `set_feature_ctrl_vmx_arg()` to enable VMX for virtualization. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/cpu.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74161/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set AES-NI Lock
by Subrata Banik (Code Review) 02 Apr '23

02 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Ronak Kanabar, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Ronak Kanabar, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74160 to look at the new patch set (#3). Change subject: soc/intel/meteorlake: Set AES-NI Lock ...................................................................... soc/intel/meteorlake: Set AES-NI Lock This function performs locking of the AES-NI enablement state. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74160/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Gerrit-Change-Number: 74160 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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