coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/common: Order the different types of cores based on APIC IDs
by Jan Samek (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Subrata Banik, Sridhar Siricilla, Kyösti Mälkki, Elyes Haouas. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72132 ) Change subject: soc/intel/common: Order the different types of cores based on APIC IDs ...................................................................... Patch Set 17: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72132/comment/8bfc2a72_2103f908 PS17, Line 13: cat Not the cat, please. https://review.coreboot.org/c/coreboot/+/72132/comment/30ee6d16_218fb5c7 PS17, Line 13: cpu$c This variable is now undefined. Use glob (`cpu*`) instead. https://review.coreboot.org/c/coreboot/+/72132/comment/165f4d22_f2a4202e PS17, Line 37: grep . cat /sys/devices/system/cpu/cpu$c/topology/thread_siblings_list ditto -- To view, visit https://review.coreboot.org/c/coreboot/+/72132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Gerrit-Change-Number: 72132 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 05 Apr 2023 08:26:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp/acpi: Fix _OSC method
by Patrick Rudolph (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Hello Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74231 to look at the new patch set (#2). Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method ...................................................................... soc/intel/xeon_sp/acpi: Fix _OSC method Fix a couple of bugs in the _OSC method for handling "PCI Host Bridge Device" on Xeon-SP. - Drop the Sleep. The code doesn't write to hardware at all, so there's no need to sleep here. - Make sure that the number of DWORD passed in Arg2 is at least 3. The existing check was useless as it would not create the DWordField, but then use it anyways. - Add check for CXL 2 device method calls which provide a 5 DWORD long buffer to prevent buffer overflows when invoking the "PCI Host Bridge Device" method. Test: Boot on Archer City and confirm that no ACPI errors are reported for _OSC. Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl 3 files changed, 54 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/74231/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Gerrit-Change-Number: 74231 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/common: Order the different types of cores based on APIC IDs
by Sridhar Siricilla (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Subrata Banik, Sridhar Siricilla, Kyösti Mälkki, Elyes Haouas. Hello build bot (Jenkins), Subrata Banik, Ronak Kanabar, Sukumar Ghorai, Kyösti Mälkki, Elyes Haouas, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72132 to look at the new patch set (#17). Change subject: soc/intel/common: Order the different types of cores based on APIC IDs ...................................................................... soc/intel/common: Order the different types of cores based on APIC IDs Currently coreboot presents the BSP core first, then efficient cores and Performance cores as indicated below: ``` grep . cat /sys/devices/system/cpu/cpu$c/topology/thread_siblings_list 0-1 4 5 6 7 0-1 2-3 2-3 ``` Existing code presents mix of different cores to OS and causes CPU load balancing and power/performance impact. So, the patch fixes this disorder by ordering the Performance cores first, compute die efficient cores next, and finally SOC efficient cores if they are present. This is done to run the media applications in a power efficient manner, please refer thae ChromeOS patch for details: https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893 BUG=b:262886449 TEST=Verified the code on Rex system After the fix: ``` grep . cat /sys/devices/system/cpu/cpu$c/topology/thread_siblings_list 0-1 0-1 2-3 2-3 4 5 6 7 ``` Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 3 files changed, 90 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/72132/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/72132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Gerrit-Change-Number: 72132 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp/acpi: Fix _OSC method
by Patrick Rudolph (Code Review) 05 Apr '23

05 Apr '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74231 ) Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method ...................................................................... soc/intel/xeon_sp/acpi: Fix _OSC method Fix a couple of bugs in the _OSC method for handling "PCI Host Bridge Device" on Xeon-SP. - Drop the Sleep. The code doesn't write to hardware at all, so there's no need to sleep here. - Make sure that the number of DWORD passed in Arg2 is at least 3. The existing check was useless as it would not create the DWordField, but then use it anyways. - Add check for CXL 2 device method calls which provide a 5 DWORD long buffer to prevent buffer overflows when invoking the "PCI Host Bridge Device" method. Test: Boot on Archer City and confirm that no ACPI errors are reported for _OSC. Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl 3 files changed, 54 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/74231/1 diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index 91a5c6c..390ff3c 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -27,11 +27,13 @@ CreateDWordField (Arg3, 0x00, CDW1) \ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ { \ - CreateDWordField (Arg3, 0x04, CDW2) \ - If ((Arg2 > 0x02)) \ + If (Arg2 < 0x03) \ { \ - CreateDWordField (Arg3, 0x08, CDW3) \ + CDW1 |= 0x02 /* Unknown failure */ \ + Return (Arg3) \ } \ + CreateDWordField (Arg3, 0x04, CDW2) \ + CreateDWordField (Arg3, 0x08, CDW3) \ SUPP = CDW2 \ CTRL = CDW3 \ If ((AHPE || ((SUPP & 0x16) != 0x16))) \ diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 299247f..ccd6234 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -43,21 +43,26 @@ || Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL */ { - CreateDWordField (Arg3, 0x04, CDW2) - If (Arg2 > 0x02) + If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */ { - CreateDWordField (Arg3, 0x08, CDW3) - CreateDWordField (Arg3, 0x0C, CDW4) - CreateDWordField (Arg3, 0x10, CDW5) + CDW1 |= 0x02 /* Unknown failure */ + Return (Arg3) } + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 CTRL = CDW3 - SUPC = CDW4 - CTRC = CDW5 + If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) + { + CreateDWordField (Arg3, 0x0C, CDW4) + CreateDWordField (Arg3, 0x10, CDW5) + SUPC = CDW4 + CTRC = CDW5 + } If (SUPP & 0x16 != 0x16) { CTRL &= 0x1E - Sleep (0x03E8) } /* Never allow SHPC (no SHPC controller in system) */ CTRL &= 0x1D @@ -72,7 +77,10 @@ CDW1 |= 0x10 } CDW3 = CTRL - CDW5 = CTRC + If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) + { + CDW5 = CTRC + } Return (Arg3) } Else diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index 7988a16..a369b11 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -35,17 +35,19 @@ CreateDWordField (Arg3, 0x00, CDW1) If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) { - CreateDWordField (Arg3, 0x04, CDW2) - If (Arg2 > 0x02) + If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */ { - CreateDWordField (Arg3, 0x08, CDW3) + CDW1 |= 0x02 /* Unknown failure */ + Return (Arg3) } + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 CTRL = CDW3 If (SUPP & 0x16 != 0x16) { CTRL &= 0x1E - Sleep (0x03E8) } /* Never allow SHPC (no SHPC controller in system) */ CTRL &= 0x1D -- To view, visit https://review.coreboot.org/c/coreboot/+/74231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Gerrit-Change-Number: 74231 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path
by Patrick Rudolph (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Michał Kopeć. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62493 ) Change subject: drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Having the device at \_SB. […] On Xeon-Sp the scope \_SB.PCI0 doesn't exist. If hardcoded it should be scope \_SB. MSDN specifies that this has to be in DSDT, but we are currently placing it in SSDT. Maybe that makes a difference? -- To view, visit https://review.coreboot.org/c/coreboot/+/62493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424 Gerrit-Change-Number: 62493 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 08:18:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
by Subrata Banik (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74207 ) Change subject: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously" ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74207/comment/0f8db242_284615bf PS2, Line 11: This initial change was causing a boot failure when transitioning into : recovery mode. > On what device? emerge-brya ?? aka brya device > What kind of failure? boot failure -- To view, visit https://review.coreboot.org/c/coreboot/+/74207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Gerrit-Change-Number: 74207 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 08:13:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Eric Lai (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/myst/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74093/comment/eb113495_a4e97c0a PS2, Line 16: Name(LIDS, 0) > The LIDS object is used by the EC and not by the SoC. […] oh I see now. It's Intel SOC use the LIDS in their GNVS. But AMD doesn't need that. Also the EC code will store it to the global LIDS. IMHO, this can add when enable chrome EC, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 9 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 08:11:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
by Paul Menzel (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74207 ) Change subject: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously" ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74207/comment/7bed173d_3fd40540 PS2, Line 11: This initial change was causing a boot failure when transitioning into : recovery mode. On what device? What kind of failure? -- To view, visit https://review.coreboot.org/c/coreboot/+/74207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Gerrit-Change-Number: 74207 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 08:00:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cmnlb/include/ts_ser: Add Pre-reset boot timestamps' IDs
by Paul Menzel (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Jay Patel. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72889 ) Change subject: cmnlb/include/ts_ser: Add Pre-reset boot timestamps' IDs ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72889/comment/dfa4c25f_00694fee PS6, Line 7: cmnlb/include/ts_ser *commonlib* would be enough as prefix in my opinion. -- To view, visit https://review.coreboot.org/c/coreboot/+/72889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503dedcd574d13cf958be19bd613f7f9f3ba8163 Gerrit-Change-Number: 72889 Gerrit-PatchSet: 6 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 07:54:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex
by Paul Menzel (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Tarun Tuli, Jamie Ryu, Wonkyu Kim, Kapil Porwal, Jay Patel. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73192 ) Change subject: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73192/comment/51b4caad_d3189689 PS6, Line 2: jaypatel256 Please use your name. https://review.coreboot.org/c/coreboot/+/73192/comment/293c905f_7fd626d0 PS6, Line 15: jaypatel256 Ditto. -- To view, visit https://review.coreboot.org/c/coreboot/+/73192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b773fb4c7abfcb3c3ab061d970327987536fb2 Gerrit-Change-Number: 73192 Gerrit-PatchSet: 6 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 07:53:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023