coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into cbmem table
by Dinesh Gehlot (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74256 to look at the new patch set (#9). Change subject: soc/intel/: Store CSE firmware version into cbmem table ...................................................................... soc/intel/: Store CSE firmware version into cbmem table The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called either from RAMSTAGE or ROMSTAGE based on underlying platform. BUG=b:273661726 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 9 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/apollolake: Communicate with the PMC over Trusted Sideband
by Sean Rhodes (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Arthur Heymans. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67076 ) Change subject: soc/intel/apollolake: Communicate with the PMC over Trusted Sideband ...................................................................... Patch Set 7: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/67076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide33c2deca4c254a18e4878d22e8f1279b39428e Gerrit-Change-Number: 67076 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 11 Apr 2023 09:17:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
by Patrick Rudolph (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Johnny Lin, Christian Walter, Shuo Liu, Lean Sheng Tan, Shelly Chang, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74296 ) Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/74296/comment/6e2a6854_d13c329a PS2, Line 260: ram_from_to use upper_ram_end()? https://review.coreboot.org/c/coreboot/+/74296/comment/6cb6a18b_9f7c4d48 PS2, Line 261: gi_mem_size why is gi_mem_size subtracted in the !CONFIG(OCP_VPD) case? The call to fixed_mem_range_flags() below would not be executed, thus you would advertise less RAM than actually available? -- To view, visit https://review.coreboot.org/c/coreboot/+/74296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Gerrit-Change-Number: 74296 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: David Hendricks Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 09:10:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/nissa/var/yaviks: Update devicetree based on FW_CONFIG for ...
by Derek Huang (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Chen-Tsung Hsieh, Tony Huang, Robert Chen, Shou-Chieh Hsu, Shon Wang. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74261 ) Change subject: mb/google/nissa/var/yaviks: Update devicetree based on FW_CONFIG for yavilla ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/yaviks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/74261/comment/43b22bd8_d27b2066 PS7, Line 562: MLB > Hi […] It's confusing. Maybe use different FW_CONFIG filed would be better, i.e. MB_USB -- To view, visit https://review.coreboot.org/c/coreboot/+/74261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e Gerrit-Change-Number: 74261 Gerrit-PatchSet: 7 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:42:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/option.h: Implement no-op option API for SMM
by Arthur Heymans (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Benjamin Doron, Lean Sheng Tan. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73906 ) Change subject: include/option.h: Implement no-op option API for SMM ...................................................................... Patch Set 3: (1 comment) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/73906/comment/be5321b6_5f7e3355 PS3, Line 164: : config NO_OPTIONS_IN_SMM : bool "Remove use of option API from SMM" Make it opt-in rather than opt-out? -- To view, visit https://review.coreboot.org/c/coreboot/+/73906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f830f08ba42bd8e8cf1961ca83673a52be9460 Gerrit-Change-Number: 73906 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into cbmem table
by Sridhar Siricilla (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: soc/intel/: Store CSE firmware version into cbmem table ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/16ca5284_b34ebe5b PS7, Line 1089: : const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); : struct cse_fw_partition_info *version; : version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); : version->cur_cse_fw_version.major = cse_bp->fw_ver.major; : version->cur_cse_fw_version.minor = cse_bp->fw_ver.minor; : version->cur_cse_fw_version.hotfix = cse_bp->fw_ver.hotfix; : version->cur_cse_fw_version.build = cse_bp->fw_ver.build; : } : > > If coreboot refers the metadata (which is CBFS FS) for CSE Lite version, we can avoid adding store […] I can ask our team to implement this. But, just for reference, you may check implementation @ cse_check_update_status() (https://review.coreboot.org/c/coreboot/+/74256/7/src/soc/intel/common/block…) once. -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:23:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Johnny Lin (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... Patch Set 32: Code-Review+2 (1 comment) Patchset: PS28: > Should we add SPR support to Change-Id: Ie682bfa376d699c0eee8de0752cd6ae6d8d81fee? CB:74297 added. -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 32 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:21:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
by Johnny Lin (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Christian Walter, Shuo Liu, Lean Sheng Tan, Shelly Chang, Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74296 ) Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74296/comment/2416c99a_dddbe4b4 PS1, Line 7: samll > small Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Gerrit-Change-Number: 74296 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: David Hendricks Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:17:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
by Johnny Lin (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Johnny Lin, Christian Walter, Shuo Liu, Shelly Chang, Tim Chu. Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Christian Walter, Shuo Liu, Lean Sheng Tan, Shelly Chang, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74296 to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled ...................................................................... soc/intel/xeon_sp: Fix very small total memory when CXL is enabled Processor attached memory should use ram_from_to rather than reserved_ram_from_to. Treat the calculation of gi_mem_size size as 64MB. By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 32 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/74296/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Gerrit-Change-Number: 74296 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: David Hendricks Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into cbmem table
by Subrata Banik (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: soc/intel/: Store CSE firmware version into cbmem table ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/31a386b5_8bd006e6 PS7, Line 1089: : const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); : struct cse_fw_partition_info *version; : version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); : version->cur_cse_fw_version.major = cse_bp->fw_ver.major; : version->cur_cse_fw_version.minor = cse_bp->fw_ver.minor; : version->cur_cse_fw_version.hotfix = cse_bp->fw_ver.hotfix; : version->cur_cse_fw_version.build = cse_bp->fw_ver.build; : } : > If coreboot refers the metadata (which is CBFS FS) for CSE Lite version, we can avoid adding store_cse_rw_fw_version() multiple times. can this be taken care by you or Intel team over an incremental CL?I don't know what this metedata looks like and where it is getting stored? -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:15:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2023