coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Felix Singer (Code Review) 11 Apr '23

11 Apr '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... mb/lenovo/x200: Read EDID in mainboard_vbt_filename() mainboard_vbt_filename() used to assume that it is called after a call to get_blc_pwm_freq_value() with a valid parameter, but currently it is the first call of get_blc_pwm_freq_value(NULL), and will return 0, so "data_led.vbt" is always returned, regardless of the actual type of the panel. Combined with the previous commit, in this commit mainboard_vbt_filename() will explicitly read EDID string via gm45_get_lvds_edid_str() and use this string to call get_blc_pwm_freq_value(). Resolves: https://ticket.coreboot.org/issues/475 Tested on my x200s with LTD121EQ3B (LED), and x200 with LTD121EWVB (CCFL). Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74181 Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/lenovo/x200/blc.c 1 file changed, 34 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Swift Geek (Sebastian Grzywna): Looks good to me, approved Bill XIE: Looks good to me, approved Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lenovo/x200/blc.c b/src/mainboard/lenovo/x200/blc.c index ef2dbb1..c03b3e9 100644 --- a/src/mainboard/lenovo/x200/blc.c +++ b/src/mainboard/lenovo/x200/blc.c @@ -4,6 +4,7 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <northbridge/intel/gm45/gm45.h> +#include <device/pci.h> #include <drivers/intel/gma/opregion.h> static const struct blc_pwm_t blc_entries[] = { @@ -36,9 +37,8 @@ const char *mainboard_vbt_filename(void) { - u16 pwm_freq; - - pwm_freq = get_blc_pwm_freq_value(NULL); + struct device *gma = pcidev_path_on_root(PCI_DEVFN(0x2, 0)); + u16 pwm_freq = gma ? get_blc_pwm_freq_value(gm45_get_lvds_edid_str(gma)) : 0; if (pwm_freq == 0) { printk(BIOS_DEBUG, -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 10 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Felix Singer (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Paul Menzel, Alexander Couzens. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 9 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 11 Apr 2023 11:46:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device: Correct D3Cold Kconfig option
by Sean Rhodes (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Kapil Porwal. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74328 ) Change subject: device: Correct D3Cold Kconfig option ...................................................................... Patch Set 2: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/74328/comment/426dc463_3c505cea PS1, Line 1012: don't > remove? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bdb6589e98ac81d0ce25df52fb916b5c2fd0157 Gerrit-Change-Number: 74328 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 11:43:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device: Correct D3Cold Kconfig option
by Kapil Porwal (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sean Rhodes. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74328 ) Change subject: device: Correct D3Cold Kconfig option ...................................................................... Patch Set 1: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/74328/comment/66be7552_1d8f6032 PS1, Line 1012: don't remove? -- To view, visit https://review.coreboot.org/c/coreboot/+/74328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bdb6589e98ac81d0ce25df52fb916b5c2fd0157 Gerrit-Change-Number: 74328 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 11 Apr 2023 11:42:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 11 Apr '23

11 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74254 ) Change subject: mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB ...................................................................... mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd 1 file changed, 54 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd index bd250f5f..6ca1cc6 100644 --- a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd @@ -4,39 +4,47 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7604K { + RW_SECTION_A 7680K { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 4400K } - RW_MISC 152K { - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - UNIFIED_MRC_CACHE(PRESERVE) 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7604K { + RW_SECTION_B 7680K { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 4400K } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K - RO_GSCVD 8K + RO_SECTION { FMAP 2K RO_FRID 64 -- To view, visit https://review.coreboot.org/c/coreboot/+/74254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Gerrit-Change-Number: 74254 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 11 Apr '23

11 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74253 ) Change subject: mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MB ...................................................................... mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MB This patch updates the Rex debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4ab69eb24937d58c8bc5d3c0a6e5cb70b843a1ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74253 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/chromeos-debug-fsp.fmd 1 file changed, 53 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/chromeos-debug-fsp.fmd b/src/mainboard/google/rex/chromeos-debug-fsp.fmd index bd250f5f..c3c1336 100644 --- a/src/mainboard/google/rex/chromeos-debug-fsp.fmd +++ b/src/mainboard/google/rex/chromeos-debug-fsp.fmd @@ -4,37 +4,45 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7604K { + RW_SECTION_A 7680K { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 4400K } - RW_MISC 152K { - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - UNIFIED_MRC_CACHE(PRESERVE) 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7604K { + RW_SECTION_B 7680K { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 4400K } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_GSCVD 8K RO_SECTION { -- To view, visit https://review.coreboot.org/c/coreboot/+/74253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab69eb24937d58c8bc5d3c0a6e5cb70b843a1ae Gerrit-Change-Number: 74253 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 11 Apr '23

11 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74252 ) Change subject: mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB ...................................................................... mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74252 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/intel/mtlrvp/chromeos.fmd 1 file changed, 56 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index 22dbff5..a5bc538 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -4,34 +4,45 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7092K { + RW_SECTION_A 7M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 4400K } - RW_MISC 152K { - UNIFIED_MRC_CACHE 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - } - RW_SECTION_B 7092K { + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 4400K } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } RW_LEGACY(CBFS) 1M + RW_UNUSED 3M # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K -- To view, visit https://review.coreboot.org/c/coreboot/+/74252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 Gerrit-Change-Number: 74252 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 11 Apr '23

11 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74229 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB ...................................................................... mb/google/rex: Update Flash Layout to fit WP_RO within 4MB This patch updates the Rex flash layout to optimize WP_RO to 4MB. The idea is to create more space inside FW_RW_A/B to accommodate multiple blobs to boot google/rex with different Intel MTL SoC stepping. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74229 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/chromeos.fmd 1 file changed, 55 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/chromeos.fmd b/src/mainboard/google/rex/chromeos.fmd index 3521232..b2c0e84 100644 --- a/src/mainboard/google/rex/chromeos.fmd +++ b/src/mainboard/google/rex/chromeos.fmd @@ -4,38 +4,45 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7092K { + RW_SECTION_A 7M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 4400K } - RW_MISC 152K { - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - UNIFIED_MRC_CACHE(PRESERVE) 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7092K { + RW_SECTION_B 7M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 4400K } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } RW_LEGACY(CBFS) 1M + RW_UNUSED 3M # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_GSCVD 8K RO_SECTION { -- To view, visit https://review.coreboot.org/c/coreboot/+/74229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Gerrit-Change-Number: 74229 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD
by Patrick Rudolph (Code Review) 11 Apr '23

11 Apr '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74339 ) Change subject: soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD ...................................................................... soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD The Kconfig is only used in common code to gather the build time maximum socket number FSP support. The same information is available in FSP header as MAX_SOCKET, thus use the FSP as truth of source. Currently MAX_SOCKET is 4. Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/romstage.c 2 files changed, 22 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/74339/1 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 832aab5..15b915d 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -27,14 +27,6 @@ string default "\\_SB.C%03X" -config MAX_SOCKET_UPD - int - default 2 - help - This is used for configuring common SPR UPD tables which their sizes - depend on the socket number. Since it's the maximal socket number for - the common UPD tables, mainboard should not overwrite it. - config SIPI_FINAL_TIMEOUT int default 400000 diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index aacc3ab..f36e5cc 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -23,8 +23,8 @@ #include "chip.h" /* Initialize to all zero first */ -static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[CONFIG_MAX_SOCKET_UPD]; -static UINT8 deemphasis_list[CONFIG_MAX_SOCKET_UPD * MAX_IIO_PORTS_PER_SOCKET]; +static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[MAX_SOCKET]; +static UINT8 deemphasis_list[MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET]; void __weak mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -119,12 +119,12 @@ unsigned int port, socket; mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table; - mupd->FspmConfig.IioPcieConfigTableNumber = CONFIG_MAX_SOCKET_UPD; + mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = (UPD_IIO_PCIE_PORT_CONFIG *)spr_iio_bifur_table; /* Initialize non-zero default UPD values */ - for (socket = 0; socket < CONFIG_MAX_SOCKET_UPD; socket++) { + for (socket = 0; socket < MAX_SOCKET; socket++) { for (port = 0; port < MAX_IIO_PORTS_PER_SOCKET; port++) { PciePortConfig[socket].PcieMaxPayload[port] = 0x7; /* Auto */ PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */ @@ -134,10 +134,10 @@ } mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list; - mupd->FspmConfig.DeEmphasisNumber = CONFIG_MAX_SOCKET_UPD * MAX_IIO_PORTS_PER_SOCKET; + mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list; - for (port = 0; port < CONFIG_MAX_SOCKET_UPD * MAX_IIO_PORTS_PER_SOCKET; port++) + for (port = 0; port < MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; port++) DeEmphasisConfig[port] = 0x1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36 Gerrit-Change-Number: 74339 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
by Subrata Banik (Code Review) 11 Apr '23

11 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74293 ) Change subject: soc/intel/{adl, cmn}: Send CSE EOP Async CMD early ...................................................................... soc/intel/{adl, cmn}: Send CSE EOP Async CMD early This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample whichcauses idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/marasov EVT sku to ChromeOS and observed ~30ms of boot time savings (across warm and cold reset scenarios). Without this patch: 963:returning from FspMultiPhaseSiInit 907,326 (97,293) ... ... 115:finished elog init 967,343 (2,581) 942:before sending EOP to ME 967,821 (478) … 16:finished LZMA decompress (ignore for x86) 1,017,937 (12,135) 943:after sending EOP to ME 1,067,799 (49,861) … … 1101:jumping to kernel 1,144,587 (13,734) Total Time: 1,144,549 With this patch: 963:returning from FspMultiPhaseSiInit 918,291 (97,320) 942:before sending EOP to ME 918,522 (230) ... ... 16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483) 943:after sending EOP to ME 1,033,456 (3,980) ... ... 1101:jumping to kernel 1,111,410 (14,007) Total Time: 1,111,375 Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/common/block/cse/cse.c 2 files changed, 71 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index e0aa983..25b412e 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -203,7 +203,8 @@ * current boot sequence) to reduce message response time from CSE hence moving * sending EOP to earlier stage. */ - if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) { + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) { printk(BIOS_INFO, "Sending EOP early from SoC\n"); cse_send_end_of_post(); } diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 6c4bb73..1aa3454 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1424,22 +1424,23 @@ */ static void cse_final(struct device *dev) { - /* SoC user decided to send EOP late */ - if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + /* + * SoC user can have two options for sending EOP: + * 1. Choose to send EOP late + * 2. Choose to send EOP cmd asynchronously + * + * In case of sending EOP in asynchronous mode, the EOP command + * has most likely not been completed yet. The finalization steps + * will be run once the EOP command has successfully been completed. + */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) return; /* 1. Send EOP to CSE if not done.*/ if (CONFIG(SOC_INTEL_CSE_SET_EOP)) cse_send_end_of_post(); - /* - * In asynchronous mode, the EOP command has most likely not been - * completed yet. Finalization steps will be run once the EOP command - * has successfully been completed. - */ - if (CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) - return; - if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) cse_final_ready_to_boot(); -- To view, visit https://review.coreboot.org/c/coreboot/+/74293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1 Gerrit-Change-Number: 74293 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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