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Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
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Patch Set 4: Code-Review+1
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Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74296/comment/43e73760_e59018b6
PS2, Line 12: By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
> Please add a blank line between paragraphs.
Done
https://review.coreboot.org/c/coreboot/+/74296/comment/92eea8bd_20a3c007
PS2, Line 13: small total memory issue
> Please elaborate.
Done
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/74296/comment/93447fc3_bb5e3c9c
PS2, Line 260: ram_from_to
> use upper_ram_end()?
Done
https://review.coreboot.org/c/coreboot/+/74296/comment/f208c7eb_a3c977ae
PS2, Line 261: gi_mem_size
> why is gi_mem_size subtracted in the !CONFIG(OCP_VPD) case? […]
gi_mem_size will be 0 if there's no CXL memory and it's subtracted no matter CONFIG(OCP_VPD) is selected or not. If there's no CXL memory, pds.pds[i].pd_type is always equals to PD_TYPE_PROCESSOR and will be skipped without executing fixed_mem_range_flags() below, the fixed_mem_range_flags() is only for CXL memory.
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Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Christian Walter, Shuo Liu, Lean Sheng Tan, Shelly Chang, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74296
to look at the new patch set (#4).
Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
......................................................................
soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
Processor attached memory should not use reserved_ram_from_to and
treat the calculation of gi_mem_size size as 64MB.
By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
this should fix small total memory issue. Before the fix running
command 'free -g -h' under Linux shows the total memory is only 1.4Gi,
after the fix it's showing the expected total memory size 15Gi.
Tested=On AC without attaching CXL memory, the total memory size is
the same as de-selecting SOC_INTEL_HAS_CXL.
Change-Id: I38e9d138fd284620ac616a65f444e943f1774869
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 34 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/74296/4
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Change subject: amdfwtool: Add --fsp-version option
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> No problem, I will print the versions to the standard out. […]
They look not very user readable at first, but amdfwtool seems more like a helper tool used in scripts and is not operated by users, so I’d be fine with it. Maybe others have a better idea.
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Change subject: [Test] Add GTCH7503 and seperate touchscreen based on SSFC.
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Patch Set 1:
(1 comment)
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173874):
https://review.coreboot.org/c/coreboot/+/74298/comment/413f262a_c6201c51
PS1, Line 6:
Subject line should not end with a period.
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Change subject: mb/amd/mayan: Update the DXIO descriptors for mayan
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74191/comment/09835121_4fefc5d0
PS2, Line 7: for mayan
Redundant, as it’s in the prefix. Maybe add “… per schematics” or something similar.
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Change subject: mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz
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Patch Set 12: Code-Review+1
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Change subject: soc/intel/xeon_sp/spr: Add and enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/xeon_sp/spr/Kconfig:
https://review.coreboot.org/c/coreboot/+/74297/comment/50ea39db_69587894
PS1, Line 111: there
the
https://review.coreboot.org/c/coreboot/+/74297/comment/4d4fa15e_d998e2d3
PS1, Line 115: FSP spec violation
Please mention the version?
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