coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/amd/mayan: Update the DXIO descriptors for mayan
by Anand Vaikar (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74191 to look at the new patch set (#2). Change subject: mb/amd/mayan: Update the DXIO descriptors for mayan ...................................................................... mb/amd/mayan: Update the DXIO descriptors for mayan Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/mayan/port_descriptors.c 1 file changed, 82 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/74191/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e Gerrit-Change-Number: 74191 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: device: Change NO_S0IX_SUPPORT default to def_bool
by Lean Sheng Tan (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sean Rhodes. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74331 ) Change subject: device: Change NO_S0IX_SUPPORT default to def_bool ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc824c3e06019c8922616c1cb83df95c10e285fc Gerrit-Change-Number: 74331 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:12:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Remove the tcss_d3_cold_disable devicetree option
by Lean Sheng Tan (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74330 ) Change subject: soc/intel/alderlake: Remove the tcss_d3_cold_disable devicetree option ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib84814bd608742680cea7c8012011b56b8fb3271 Gerrit-Change-Number: 74330 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:11:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Move TCSS D3 Cold to Kconfig
by Lean Sheng Tan (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Kapil Porwal. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74329 ) Change subject: soc/intel/meteorlake: Move TCSS D3 Cold to Kconfig ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb22188ac5089e2ecf00850b2da8500ab73d6c2 Gerrit-Change-Number: 74329 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:10:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device: Correct D3Cold Kconfig option
by Lean Sheng Tan (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sean Rhodes. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74328 ) Change subject: device: Correct D3Cold Kconfig option ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bdb6589e98ac81d0ce25df52fb916b5c2fd0157 Gerrit-Change-Number: 74328 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:10:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into cbmem table
by Sridhar Siricilla (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: soc/intel/: Store CSE firmware version into cbmem table ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/7f1ff026_24e13116 PS7, Line 1089: : const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); : struct cse_fw_partition_info *version; : version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); : version->cur_cse_fw_version.major = cse_bp->fw_ver.major; : version->cur_cse_fw_version.minor = cse_bp->fw_ver.minor; : version->cur_cse_fw_version.hotfix = cse_bp->fw_ver.hotfix; : version->cur_cse_fw_version.build = cse_bp->fw_ver.build; : } : > Make sense as per the flow. […] If coreboot refers the metadata (which is CBFS FS) for CSE Lite version, we can avoid adding store_cse_rw_fw_version() multiple times. -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:06:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Johnny Lin (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang. Johnny Lin has uploaded a new patch set (#32) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... mb/intel: Add 2 SPR sockets CRB Archer City Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes Emmitsburg PCH. It was tested with LinuxBoot payload on both dual and single socket configurations. The multisocket support depends on Change-Id: I4a593252bb7f68494f4ccce215ac9cf1eb19b190 Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 483 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 32 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add and enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS
by Johnny Lin (Code Review) 11 Apr '23

11 Apr '23

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74297 ) Change subject: soc/intel/xeon_sp/spr: Add and enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS ...................................................................... soc/intel/xeon_sp/spr: Add and enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS Change-Id: I4a593252bb7f68494f4ccce215ac9cf1eb19b190 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/74297/1 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 832aab5..455d7fc 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -103,6 +103,17 @@ documentation says this needs to be at least 128KiB, but practice show this needs to be 256KiB or more. +config BROKEN_FSP_NEEDS_STACK_ABOVE_BSS + bool + default y + depends on FSP_USES_CB_STACK + help + Starting with Intel CPX there is a bug in there reference code during + the Pipe init. This code synchronises the CAR between sockets in FSP-M. + The code implicitly assumes that the stack in use is above the FSP heap, + which is confusingly configured with FspStackBase. This issue is only + present on multi socket systems. This is a FSP spec violation. + config IED_REGION_SIZE hex default 0x400000 -- To view, visit https://review.coreboot.org/c/coreboot/+/74297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a593252bb7f68494f4ccce215ac9cf1eb19b190 Gerrit-Change-Number: 74297 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into cbmem table
by Subrata Banik (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: soc/intel/: Store CSE firmware version into cbmem table ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/57887d9c_3fa5cd3d PS8, Line 1082: SOC_INTEL_CSE_LITE_SKU > This flag check is not required since the file get compiled only if SOC_INTEL_CSE_LITE_SKU config is selected. +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 08:00:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled
by Lean Sheng Tan (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Johnny Lin, Christian Walter, Shuo Liu, Shelly Chang, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74296 ) Change subject: soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74296/comment/08f464ba_a79227c8 PS1, Line 7: samll small -- To view, visit https://review.coreboot.org/c/coreboot/+/74296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Gerrit-Change-Number: 74296 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: David Hendricks Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:55:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023