coreboot-gerrit April 2023

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[M] Change in coreboot[master]: arch/x86/ioapic: Promote ioapic_get_sci_pin()
by Kyösti Mälkki (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74337 ) Change subject: arch/x86/ioapic: Promote ioapic_get_sci_pin() ...................................................................... arch/x86/ioapic: Promote ioapic_get_sci_pin() Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/ioapic.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 25 files changed, 46 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/74337/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index b7831e1..cf96aee 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -207,7 +207,7 @@ } #endif -u16 acpi_sci_int(void) +static u16 acpi_sci_int(void) { #if ENV_X86 u8 gsi, irq, flags; @@ -1709,6 +1709,8 @@ if (CONFIG(USE_PC_CMOS_ALTCENTURY)) fadt->century = RTC_CLK_ALTCENTURY; + fadt->sci_int = acpi_sci_int(); + arch_fill_fadt(fadt); acpi_fill_fadt(fadt); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index c143ef5..739178f 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1350,8 +1350,6 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current); -u16 acpi_sci_int(void); - int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 08effca..6bcc605 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -49,8 +49,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 09c35db..c71c863 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -34,6 +34,13 @@ pm_write8(PM_SERIRQ_CONF, byte); } +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW; +} + static void fch_ioapic_init(void) { fch_enable_ioapic_decode(); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index cb8039d..6cf5536 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -52,8 +52,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 17d8955..f459388 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -51,8 +51,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 5e37a27..9ebe353 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -52,8 +52,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 227a5d8..33defac 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -57,8 +57,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 947c806..97d2dce 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -51,8 +51,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index a76d161..c01a79a 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> #include "chip.h" @@ -11,8 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_int(); - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index a76d161..d071b92 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -11,8 +11,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_int(); - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 9355670..2ffebc3 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -10,8 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = 9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 953b03f..f692b41 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -94,8 +94,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_int(); - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 4989d6b..0dacad2 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -26,8 +26,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE); - fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (permanent_smi_handler()) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 79d1005..89a3057 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -19,6 +19,13 @@ * HUDSON enables SATA by default in SMBUS Control. */ +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW; +} + static void sm_init(struct device *dev) { setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index f625198..fe9687f 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -12,8 +12,6 @@ struct southbridge_intel_bd82x6x_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index fe61af1..2fc1445 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -52,6 +52,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c +ramstage-y += ioapic.c + smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c diff --git a/src/southbridge/intel/common/ioapic.c b/src/southbridge/intel/common/ioapic.c new file mode 100644 index 0000000..1dfc4f6 --- /dev/null +++ b/src/southbridge/intel/common/ioapic.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/ioapic.h> +#include <stdint.h> + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; +} diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 1d640f4..0023406 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -17,8 +17,6 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - fadt->sci_int = 9; - if (permanent_smi_handler()) { /* TODO: SMI handler is not implemented. */ fadt->smi_cmd = 0x00; diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index fdb7fb3..ac214d9 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -8,8 +8,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 6d63e72..621bf68 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -14,8 +14,6 @@ struct southbridge_intel_i82801gx_config *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 54ebcbd..8005fe1 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -10,8 +10,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 9d60ca5a..005fdb6 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -10,8 +10,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index 13243af..d337e3e 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -12,8 +12,6 @@ struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index 2051223..a4b537d 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -12,8 +12,6 @@ struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; u16 pmbase = get_pmbase(); - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/74337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Gerrit-Change-Number: 74337 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel: Introduce ioapic_get_sci_pin()
by Kyösti Mälkki (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74326 to look at the new patch set (#2). Change subject: soc/intel: Introduce ioapic_get_sci_pin() ...................................................................... soc/intel: Introduce ioapic_get_sci_pin() According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. It appears touched platforms currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/arch/x86/include/arch/ioapic.h M src/include/acpi/acpi.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/common/block/acpi/acpi.c 10 files changed, 122 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/74326/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Gerrit-Change-Number: 74326 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Eric Lai (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rex/variants/baseboard/rex/gpio.c: https://review.coreboot.org/c/coreboot/+/74257/comment/8c45b3b8_8f415304 PS3, Line 32: DECLARE_WEAK_CROS_GPIOS(cros_gpios); > you can remove it and just use DECLARE_NO_CROS_GPIOS for template oh can't do that since no _WEAK for that maybe just put empty array. -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:51:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into cbmem table
by Sridhar Siricilla (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: soc/intel/: Store CSE firmware version into cbmem table ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/1ffe2460_8ae76ff4 PS7, Line 1089: : const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); : struct cse_fw_partition_info *version; : version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); : version->cur_cse_fw_version.major = cse_bp->fw_ver.major; : version->cur_cse_fw_version.minor = cse_bp->fw_ver.minor; : version->cur_cse_fw_version.hotfix = cse_bp->fw_ver.hotfix; : version->cur_cse_fw_version.build = cse_bp->fw_ver.build; : } : > > Can't this be handled in the cse_get_bp_info() itself? Doing so, we can avoid resending the comman […] Make sense as per the flow. Instead of sending HECI command to get CSE Lite version, coreboot can track CSE Lite version in the metadata. File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/081996da_f1b2d87b PS8, Line 1082: SOC_INTEL_CSE_LITE_SKU This flag check is not required since the file get compiled only if SOC_INTEL_CSE_LITE_SKU config is selected. -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:50:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Eric Lai (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rex/variants/baseboard/rex/gpio.c: https://review.coreboot.org/c/coreboot/+/74257/comment/dc8060df_b63db03f PS3, Line 32: DECLARE_WEAK_CROS_GPIOS(cros_gpios); you can remove it and just use DECLARE_NO_CROS_GPIOS for template -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:47:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: amdfwtool: Add --fsp-version option
by Grzegorz Bernacki (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Paul Menzel, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Grzegorz Bernacki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74266 ) Change subject: amdfwtool: Add --fsp-version option ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74266/comment/7fcaea9c_4b9d2e15 PS1, Line 9: This version tells amdfwtool to create a text file : which contains versions of following blobs: : PSP bootloader (type 0x01), : SMU firmware (type 0x08), : AGESA bootloader 0 (type 0x30). > > Passing this option tells amdfwtool to create a text file, […] OK, I rephrase according to requested changes. https://review.coreboot.org/c/coreboot/+/74266/comment/309c63d7_bb0f6d98 PS1, Line 14: > What is the new switch/option going to be used for? Maybe start with the motivation. Sure, I'll add it https://review.coreboot.org/c/coreboot/+/74266/comment/528d0736_63087d50 PS1, Line 16: TEST=Tested on Skyrim device > If possible, please paste the commands and the output: […] Yes, I'll add it in the next version Patchset: PS1: > As I do not know, what the option is going to be used for, I think the KISS way would be to just out […] No problem, I will print the versions to the standard out. What do you think about --print-type0x01-version, --print-type0x08-version and so on? -- To view, visit https://review.coreboot.org/c/coreboot/+/74266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Gerrit-Change-Number: 74266 Gerrit-PatchSet: 1 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:46:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled
by Johnny Lin (Code Review) 11 Apr '23

11 Apr '23

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74296 ) Change subject: soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled ...................................................................... soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled Processor attached memory should use ram_from_to rather than reserved_ram_from_to. Treat the calculation of gi_mem_size size as 64MB. By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 32 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/74296/1 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 5249a94..2a4cf5c 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -249,18 +249,22 @@ if (CONFIG(SOC_INTEL_HAS_CXL)) { /* 4GiB -> CXL Memory */ uint32_t gi_mem_size; - gi_mem_size = get_generic_initiator_mem_size(); - - res = reserved_ram_from_to(dev, index++, 0x100000000, - mc_values[TOHM_REG] - (uint64_t)gi_mem_size + 1); + gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ + /* + * Memory layout when there is CXL HDM (Host-managed Device Memory): + * -------------- <- TOHM + * CXL memory regions (pds global variable records the base/size of them) + * Processor attached high memory + * -------------- <- 0x100000000 (4GB) + */ + res = ram_from_to(dev, index++, 0x100000000, + mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); LOG_RESOURCE("high_ram", dev, res); - /* CXL Memory */ uint8_t i; for (i = 0; i < pds.num_pds; i++) { if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) continue; - if (CONFIG(OCP_VPD)) { unsigned long flags = IORESOURCE_CACHEABLE; int cxl_mode = get_cxl_mode_from_vpd(); @@ -269,8 +273,9 @@ else flags |= IORESOURCE_STORED; - res = fixed_mem_range_flags(dev, index++, (uint64_t)pds.pds[i].base, - (uint64_t)pds.pds[i].size, flags); + res = fixed_mem_range_flags(dev, index++, + (uint64_t)pds.pds[i].base << 26, + (uint64_t)pds.pds[i].size << 26, flags); if (cxl_mode == CXL_SPM) LOG_RESOURCE("specific_purpose_memory", dev, res); else -- To view, visit https://review.coreboot.org/c/coreboot/+/74296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Gerrit-Change-Number: 74296 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Sridhar Siricilla (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Dinesh Gehlot. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74255 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 7 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:45:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Sridhar Siricilla (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Haribalaraman Ramasubramanian, Dinesh Gehlot, Rizwan Qureshi, Reka Norman. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 27 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:45:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede: Create taranza variant
by Eric Lai (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sam McNally, David Wu, YH Lin, Lucas Chen, Ren Kuo, Zhuohao Lee, Sheng-Liang Pan. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74295 ) Change subject: mb/google/dedede: Create taranza variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id64e48ff2acd6e827fe586a00376183930ddc7e1 Gerrit-Change-Number: 74295 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 07:45:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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