coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
by Dtrain Hsu (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74335 to look at the new patch set (#4). Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx ...................................................................... mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx This patch configures external V1p05/Vnn/VnnSx rails for Uldren to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldren/overridetree.cb 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74335/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Gerrit-Change-Number: 74335 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
by Dtrain Hsu (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74335 to look at the new patch set (#3). Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx ...................................................................... mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx This patch configures external V1p05/Vnn/VnnSx rails for Uldren to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:272829190 TEST=emerge-nissa coreboot Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldren/overridetree.cb 1 file changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74335/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Gerrit-Change-Number: 74335 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
by Dtrain Hsu (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74335 ) Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/uldren/overridetree.cb: https://review.coreboot.org/c/coreboot/+/74335/comment/e07c6256_3f20babc PS1, Line 42: > trailing whitespace Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/74335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Gerrit-Change-Number: 74335 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 05:50:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
by build bot (Jenkins) (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74335 ) Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/uldren/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173853): https://review.coreboot.org/c/coreboot/+/74335/comment/b06d59fb_ff0fd0d0 PS1, Line 42: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/74335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Gerrit-Change-Number: 74335 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 05:48:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
by Dtrain Hsu (Code Review) 11 Apr '23

11 Apr '23

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74335 ) Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx ...................................................................... mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx This patch configures external V1p05/Vnn/VnnSx rails for Uldren to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:272829190 TEST=emerge-nissa coreboot Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldren/overridetree.cb 1 file changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74335/1 diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb index dbe46ed..e88389f 100644 --- a/src/mainboard/google/brya/variants/uldren/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb @@ -25,6 +25,21 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/74335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Gerrit-Change-Number: 74335 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slot
by Sridhar Siricilla (Code Review) 11 Apr '23

11 Apr '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73054 ) Change subject: mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slot ...................................................................... mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slot This change enables PCIe x1 slot. In addition, it turns off 3.3v and 12v power and assert PERST# when suspend and turn on the power and deassert the PERST# when resume for the x1 slot. NOTE: Kconfig flag and required GPIO pins are already configured. - /soc/intel/meteorlake/Kconfig select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 - gpio.c: /* GPP_A18: X1_PCIE_SLOT3_PWR_EN */ PAD_CFG_GPO(GPP_A18, 1, DEEP), /* GPP_A19: X1_DT_PCIE_RST_N */ /* SRCCLKREQ: GPP_C12: SRCCLKREQ3_GEN4_X1_DT_SLOT3_N */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), BUG=b:224325352 BRANCH=None TEST=Insert a SD card or NIC AIC on PCIe x1 slot and the AIC should be detected and enabled at boot. For S0ix, run 'suspend_stress_test -c 1'. The RP6 should not cause any suspend and resume issue. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Id2e92acf754569a22ea76a68c91aafce0075a742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73054 Reviewed-by: Harsha B R <harsha.b.r(a)intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Usha P <usha.p(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 57 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Jamie Ryu: Looks good to me, but someone else must approve Usha P: Looks good to me, approved Harsha B R: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 65da43c..e80c542 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -267,6 +267,23 @@ device generic 0 on end end end + device ref pcie_rp6 on + # Enable PCH PCIE x1 slot using CLK 3 + register "pcie_rp[PCIE_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A18)" + register "enable_delay_ms" = "100" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A19)" + register "reset_delay_ms" = "20" + register "srcclk_pin" = "3" + device generic 0 on + end + end + end # PCIE x1 slot device ref pcie_rp7 on # Enable PCH PCIE RP 7 using CLK 1 register "pcie_rp[PCIE_RP(7)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/73054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2e92acf754569a22ea76a68c91aafce0075a742 Gerrit-Change-Number: 73054 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: Reland "drivers/intel/dptf: Add multiple fan support under dptf"
by Sumeet R Pawnikar (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Lance Zhao, Subrata Banik, Caveh Jalali, Tim Wawrzynczak, Maximilian Brune, Boris Mittelberg. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73249 ) Change subject: Reland "drivers/intel/dptf: Add multiple fan support under dptf" ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73249/comment/af81ead1_0bb3b0a6 PS4, Line 7: Reland drivers/intel/dptf: Add multiple fan support under dptf > nit: please add quotes […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Gerrit-Change-Number: 73249 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 04:35:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: Reland "drivers/intel/dptf: Add multiple fan support under dptf"
by Sumeet R Pawnikar (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Lance Zhao, Subrata Banik, Caveh Jalali, Tim Wawrzynczak, Sumeet R Pawnikar, Maximilian Brune, Boris Mittelberg. Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Caveh Jalali, Reka Norman, Paul Menzel, Tim Wawrzynczak, Maximilian Brune, Lean Sheng Tan, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73249 to look at the new patch set (#5). Change subject: Reland "drivers/intel/dptf: Add multiple fan support under dptf" ...................................................................... Reland "drivers/intel/dptf: Add multiple fan support under dptf" This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e. Add multiple fan support for dptf policies. This also fixes the Google Meet resolution drop issue as per b:246535768 comment#12. When system starts Google Meet video call, it uses the hardware accelerated encoder as expected. But, as soon as another system connects to the call, an immediate fallback is observed from hardware to software encoder. Due to this, Google Meet resolution dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC based fanless platforms. This same issue was not seen on fan based systems. With the fix in dptf driver where fan configures appropriate setting for only fan participant, not for other device participants, able to see consistent 720p resolution. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alder Lake-P Redrix system for two fans support and on Alder Lake-N fanless systems. With this code change Google Meet resolution drop not observed. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/ec/google/chromeec/acpi/emem.asl M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/ec/google/chromeec/ec_dptf_helpers.c M src/ec/google/common/dptf.h M src/include/acpi/acpigen_dptf.h 9 files changed, 240 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/73249/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/73249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Gerrit-Change-Number: 73249 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Remove the tcss_d3_cold_disable devicetree option
by Eric Lai (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74330 ) Change subject: soc/intel/alderlake: Remove the tcss_d3_cold_disable devicetree option ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib84814bd608742680cea7c8012011b56b8fb3271 Gerrit-Change-Number: 74330 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 03:59:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Move TCSS D3 Cold to Kconfig
by Eric Lai (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74329 ) Change subject: soc/intel/meteorlake: Move TCSS D3 Cold to Kconfig ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb22188ac5089e2ecf00850b2da8500ab73d6c2 Gerrit-Change-Number: 74329 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 03:59:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023