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Hello build bot (Jenkins), Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74228
to look at the new patch set (#4).
Change subject: mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts
......................................................................
mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
These new memory are added for yavilla.
DRAM Part Name ID to assigna
H58G66BK7BX067 4 (0100)
MT62F2G32D4DS-026 WT:B 4 (0100)
K3KL9L90CM-MGCT 4 (0100)
H58G66AK6BX070 5 (0101)
BUG=b:277148122
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/yaviks/memory/Makefile.inc
M src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
3 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/74228/4
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Change subject: soc/amd/phoenix: Update XHCI events
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Change subject: mb/google/myst: Enable tis_plat_irq_status
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
We can move this to common code like Intel did.
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
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Change subject: rex: add variant gpio tables for variant creation
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> > Ah I see. But I am not sure the codes generated by new_variants will support this scheme? […]
I think variant creation is assuming something so it seems like what we have in place is not compatible?
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