coreboot-gerrit April 2023

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[M] Change in coreboot[master]: ACPI: Add helper for MADT LAPICs
by Kyösti Mälkki (Code Review) 11 Apr '23

11 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74312 ) Change subject: ACPI: Add helper for MADT LAPICs ...................................................................... ACPI: Add helper for MADT LAPICs This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 4 files changed, 38 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2439d7b..f4b6d20 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -122,7 +122,7 @@ return sizeof(acpi_mcfg_mmconfig_t); } -int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) +static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) { lapic->type = LOCAL_APIC; /* Local APIC structure */ lapic->length = sizeof(acpi_madt_lapic_t); @@ -133,7 +133,7 @@ return lapic->length; } -int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic) +static int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic) { lapic->type = LOCAL_X2APIC; /* Local APIC structure */ lapic->reserved = 0; @@ -145,6 +145,18 @@ return lapic->length; } +unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 index, u32 lapic_id) +{ + if (lapic_id <= ACPI_MADT_MAX_LAPIC_ID) + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index, + lapic_id); + else + current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, index, + lapic_id); + + return current; +} + static unsigned long acpi_create_madt_lapics(unsigned long current) { struct device *cpu; @@ -159,14 +171,8 @@ } if (num_cpus > 1) bubblesort(apic_ids, num_cpus, NUM_ASCENDING); - for (index = 0; index < num_cpus; index++) { - if (apic_ids[index] < 0xff) - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - index, apic_ids[index]); - else - current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, - index, apic_ids[index]); - } + for (index = 0; index < num_cpus; index++) + current = acpi_create_madt_one_lapic(current, index, apic_ids[index]); return current; } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 36201ae..77f73ae 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -682,6 +682,8 @@ u32 flags; /* Local APIC flags */ } __packed acpi_madt_lapic_t; +#define ACPI_MADT_MAX_LAPIC_ID 0xfe + /* MADT: Local APIC NMI Structure */ typedef struct acpi_madt_lapic_nmi { u8 type; /* Type (4) */ @@ -1334,7 +1336,6 @@ int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, u8 eniw, u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target); -int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base); int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); @@ -1343,12 +1344,11 @@ void acpi_create_madt(acpi_madt_t *madt); +unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 cpu, u32 apic); unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current); -int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); - int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 2e39f72..e18c288 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -81,14 +81,9 @@ { size_t index; - for (index = 0; index < cpu_apic_info.total_cpu_cnt; index++) { - if (cpu_apic_info.apic_ids[index] < 0xff) - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - index, cpu_apic_info.apic_ids[index]); - else - current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, - index, cpu_apic_info.apic_ids[index]); - } + for (index = 0; index < cpu_apic_info.total_cpu_cnt; index++) + current = acpi_create_madt_one_lapic(current, index, + cpu_apic_info.apic_ids[index]); return current; } diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 619e5bb..c609f4f 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -540,8 +540,7 @@ } if (!cpu->enabled) continue; - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, num_cpus, - cpu->path.apic.apic_id); + current = acpi_create_madt_one_lapic(current, num_cpus, cpu->path.apic.apic_id); num_cpus++; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592c69e0f52687924fe41189b082c86913999136 Gerrit-Change-Number: 74312 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ACPI: Add helper for MADT LAPIC NMIs
by Kyösti Mälkki (Code Review) 11 Apr '23

11 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74311 ) Change subject: ACPI: Add helper for MADT LAPIC NMIs ...................................................................... ACPI: Add helper for MADT LAPIC NMIs This avoids some code duplication related to X2APIC mode. Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/cpu_hybrid.c 3 files changed, 32 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Sridhar Siricilla: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 53b1607..2439d7b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -213,7 +213,7 @@ return irqoverride->length; } -int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, +static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint) { lapic_nmi->type = LOCAL_APIC_NMI; /* Local APIC NMI structure */ @@ -225,7 +225,7 @@ return lapic_nmi->length; } -int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, +static int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint) { lapic_nmi->type = LOCAL_X2APIC_NMI; /* Local APIC NMI structure */ @@ -240,12 +240,10 @@ return lapic_nmi->length; } -unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +unsigned long acpi_create_madt_lapic_nmis(unsigned long current) { const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH; - current = acpi_create_madt_lapics(current); - /* 1: LINT1 connect to NMI */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, @@ -258,6 +256,13 @@ return current; } +unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +{ + current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapic_nmis(current); + return current; +} + void acpi_create_madt(acpi_madt_t *madt) { acpi_header_t *header = &(madt->header); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index e99f5b9..36201ae 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1340,14 +1340,15 @@ int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); -int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint); + void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); + +unsigned long acpi_create_madt_lapic_nmis(unsigned long current); + int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); -int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, - u16 flags, u8 lint); + int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 7725e3f..2e39f72 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -95,19 +95,8 @@ unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current) { - const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH; - current = acpi_create_madt_lapics_hybrid(current); - - /* 1: LINT1 connect to NMI */ - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1); - - if (!CONFIG(XAPIC_ONLY)) - current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, - ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1); - + current = acpi_create_madt_lapic_nmis(current); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Gerrit-Change-Number: 74311 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: binaryPI: Use common code for LAPIC NMIs
by Kyösti Mälkki (Code Review) 11 Apr '23

11 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74310 ) Change subject: binaryPI: Use common code for LAPIC NMIs ...................................................................... binaryPI: Use common code for LAPIC NMIs Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74310 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/northbridge/amd/pi/00730F01/acpi_tables.c 3 files changed, 16 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2706bf7..53b1607 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -145,7 +145,7 @@ return lapic->length; } -unsigned long acpi_create_madt_lapics(unsigned long current) +static unsigned long acpi_create_madt_lapics(unsigned long current) { struct device *cpu; int index, apic_ids[CONFIG_MAX_CPUS] = {0}, num_cpus = 0; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index a108d6a..e99f5b9 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1343,7 +1343,7 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); -unsigned long acpi_create_madt_lapics(unsigned long current); + unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index d786215..1cf7e74 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -7,7 +7,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, @@ -26,9 +26,5 @@ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Gerrit-Change-Number: 74310 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Enable tis_plat_irq_status
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Eric Lai. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74286 ) Change subject: mb/google/myst: Enable tis_plat_irq_status ...................................................................... Patch Set 10: (1 comment) Patchset: PS7: > We can move this to common code like Intel did. […] b/277787305 -- To view, visit https://review.coreboot.org/c/coreboot/+/74286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Gerrit-Change-Number: 74286 Gerrit-PatchSet: 10 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 19:40:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74112 to look at the new patch set (#34). Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... mb/google/myst: Enable PCIe devices in devicetree Ensure that DXIO descriptors are updated using info from AMD and Myst board schematics. BUG=b:275960920,b:276744321 TEST=builds Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 3 files changed, 119 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74112/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 34 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Add ACPI configuration for USB ports
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Paul Menzel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74106 to look at the new patch set (#27). Change subject: mb/google/myst: Add ACPI configuration for USB ports ...................................................................... mb/google/myst: Add ACPI configuration for USB ports The USB port configuration was derived from the PPR and schematics. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras (World/User facing) 1 Bluetooth transceiver 1 WWAN BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 118 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74106/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/74106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Gerrit-Change-Number: 74106 Gerrit-PatchSet: 27 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/northbridge.asl: drop TOM1&TOM2 externals
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74302 ) Change subject: soc/amd/stoneyridge/acpi/northbridge.asl: drop TOM1&TOM2 externals ...................................................................... soc/amd/stoneyridge/acpi/northbridge.asl: drop TOM1&TOM2 externals The TOM1 and TOM2 external objects are neither needed nor used, so remove them. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8f2df272581c82a8918b06596b6a5b934028e664 --- M src/soc/amd/stoneyridge/acpi/northbridge.asl 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/74302/1 diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 7ed6225..f6044a9 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Note: Only need HID on Primary Bus */ -External (TOM1) -External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f2df272581c82a8918b06596b6a5b934028e664 Gerrit-Change-Number: 74302 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/picasso/acpi/northbridge.asl: drop unneeded TOM1&TOM2 externals
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74301 ) Change subject: soc/amd/picasso/acpi/northbridge.asl: drop unneeded TOM1&TOM2 externals ...................................................................... soc/amd/picasso/acpi/northbridge.asl: drop unneeded TOM1&TOM2 externals The TOM1 and TOM2 external objects are neither needed nor used, so remove them. TEST=Mandolin still boots and no new or possibly related ACPI errors in dmesg. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie7b5c155692d1c621546857af99b390de8a8a26e --- M src/soc/amd/picasso/acpi/northbridge.asl 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74301/1 diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 6850a1a..f9eed4e 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Note: Only need HID on Primary Bus */ -External (TOM1) -External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b5c155692d1c621546857af99b390de8a8a26e Gerrit-Change-Number: 74301 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/xeon_sp/acpi: Fix _OSC method
by 9elements QA (Code Review) 11 Apr '23

11 Apr '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74231 ) Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/158428 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/158426 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/158425 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/158424 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/158423 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/158422 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/158421 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/158420 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/158419 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/158418 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/74231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Gerrit-Change-Number: 74231 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 18:59:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/mtl: Add meteorlake B0 stepping CPU ID
by Paul Menzel (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Musse Abdullahi. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74300 ) Change subject: soc/intel/mtl: Add meteorlake B0 stepping CPU ID ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74300/comment/4d8fe35e_ff5fe792 PS1, Line 7: meteorlake Meteor Lake https://review.coreboot.org/c/coreboot/+/74300/comment/b77eb2bb_a2cc4023 PS1, Line 8: If you have the source handy, please document it in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/74300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Gerrit-Change-Number: 74300 Gerrit-PatchSet: 1 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 18:52:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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