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Change subject: soc/amd/phoenix: Update XHCI events
......................................................................
soc/amd/phoenix: Update XHCI events
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI
to allow for XHCI events to be logged.
BUG=b:277273428
TEST=builds
Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/soc/amd/phoenix/Kconfig
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3 files changed, 37 insertions(+), 2 deletions(-)
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Change subject: mb/google/myst: Disable keyboard reset pin
......................................................................
mb/google/myst: Disable keyboard reset pin
The keyboard reset is not being used on this board, so disable the
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BUG=b:277294460
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Change subject: mb/google/myst: Enable S0ix
......................................................................
mb/google/myst: Enable S0ix
Enable s0ix on Myst.
BUG=b:277215113
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Change subject: mb/google/myst: Set system type to laptop
......................................................................
mb/google/myst: Set system type to laptop
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Change subject: mb/google/myst: Configure WLAN
......................................................................
mb/google/myst: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mapping derived from myst schematic.
BUG=b:275965982
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Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
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---
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M src/mainboard/google/myst/bootblock.c
A src/mainboard/google/myst/romstage.c
M src/mainboard/google/myst/variants/baseboard/Makefile.inc
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/gpio.c
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
7 files changed, 104 insertions(+), 4 deletions(-)
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
mb/google/myst: Enable PCIe devices in devicetree
Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.
BUG=b:275960920,b:276744321
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---
M src/mainboard/google/myst/port_descriptors.c
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
3 files changed, 123 insertions(+), 1 deletion(-)
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Change subject: mb/google/myst: Add ACPI configuration for USB ports
......................................................................
Patch Set 27: Code-Review+2
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 34:
(2 comments)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/2b58a200_3dcc378c
PS31, Line 59: GEN3
> Done
GEN4
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74112/comment/6167cd3c_8f64aa66
PS31, Line 88: device ref gpp_bridge_2_1 on end # WWAN
: device ref gpp_bridge_2_2 on end # WLAN
: device ref gpp_bridge_2_3 on end # SD
: device ref gpp_bridge_2_4 on end # NVMe
: device ref iommu on end
: device ref lpc_bridge on
: chip ec/google/chromeec
: device pnp 0c09.0 alias chrome_ec on end
: end
: end
Why was this block removed? Are they added in a different CL now?
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Change subject: mb/intel/dq67sw: Add LGA1155 microATX mainboard
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> Thank you again for making this port, and also for [uploading the logs to the board status repositor […]
My pleasure, I'm happy that it got reviewed and merged! Thanks for having a look into the logs.
1. I tried the other two options ("LZ4" and "none") and they do have an effect on the size of 'fallback/payload` in the CBFS - the compressed options make them much smaller than without compression:
```
none: fallback/payload 0x448c0 simple elf 5832760 none
LZMA: fallback/payload 0x448c0 simple elf 780146 none
LZ4: fallback/payload 0x448c0 simple elf 1203966 none
```
When I extract it with e.g. `build/cbfstool build/coreboot.rom extract -n fallback/payload -f payload.lzma -m x86` then it always appears at the full size of 5840896. It seems that `cbfstool` is hiding something from us!
2. I think the correct way would be to add this to the Kconfig in a new patch?
```
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x4000
```
I tried this successfully for the ASRock H77 Pro4-M, in a local build. 0x1000 was not enough. I then checked the number of bytes in `cbmem -c1` in the lines before it says "ramstage starting":
```
$ head -n 231 4_cbmem_c1.log | wc -c
9400
```
So it seems 0x4000 is not unreasonably large, if my "calculation" is correct. It was with all four DIMM slots populated, and with the RW_MRC_CACHE empty so it did a full initialization.
3. Here I am a bit lost. If these bus addresses correlate directly with devicetree.cb entries then these should be off as per the default setting in `src/northbridge/intel/sandybridge/chipset.cb`. But I don't really understand what these warnings mean.
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Change subject: mb/google/myst: Add ACPI configuration for USB ports
......................................................................
Patch Set 27: Code-Review+1
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