coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Paul Fagerburg (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Kapil Porwal, Eric Lai. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > I think variant creation is assuming something so it seems like what we have in place is not compati […] variant creation expects things a certain way. As older boards are deprecated, we may be able to clean this up, but for now, it needs the implementation this way. -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 21:04:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: YH Lin <yueherngl(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by YH Lin (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Eric Lai. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rex/variants/baseboard/rex/gpio.c: https://review.coreboot.org/c/coreboot/+/74257/comment/6e8e3880_3c46d217 PS3, Line 32: DECLARE_WEAK_CROS_GPIOS(cros_gpios); > oh can't do that since no _WEAK for that maybe just put empty array. OK, then we are good. -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 20:51:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable XHCI controllers
by Karthik Ramasubramanian (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74105 ) Change subject: mb/google/myst: Enable XHCI controllers ...................................................................... Patch Set 26: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8 Gerrit-Change-Number: 74105 Gerrit-PatchSet: 26 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 20:49:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74303 ) Change subject: soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom ...................................................................... soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom Use the common acpi_fill_root_complex_tom function instead of the SoC- level northbridge_fill_ssdt_generator function that does basically the same. TEST=Resulting coreboot SSDT remains unchanged on Careena. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie0f100e0766ce0f826daceba7dbec1fb88492938 --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 18 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/74303/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 7913827..b1d2bdd 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <amdblocks/acpi.h> #include <amdblocks/biosram.h> #include <amdblocks/hda.h> #include <device/pci_ops.h> @@ -186,27 +187,6 @@ return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(const struct device *device) -{ - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_pop_len(); -} - static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -285,7 +265,7 @@ .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .acpi_fill_ssdt = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = acpi_fill_root_complex_tom, .write_acpi_tables = agesa_write_acpi_tables, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/74303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0f100e0766ce0f826daceba7dbec1fb88492938 Gerrit-Change-Number: 74303 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/northbridge.asl: drop TOM1&TOM2 externals
by Matt DeVillier (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74302 ) Change subject: soc/amd/stoneyridge/acpi/northbridge.asl: drop TOM1&TOM2 externals ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: these objects are generated in SSDT via src/soc/amd/common/block/acpi/tables.c, and TOM1 is referenced in src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl. TOM2 can probably be dropped though. -- To view, visit https://review.coreboot.org/c/coreboot/+/74302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f2df272581c82a8918b06596b6a5b934028e664 Gerrit-Change-Number: 74302 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 Apr 2023 20:36:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Add smihandler
by Raul Rangel (Code Review) 11 Apr '23

11 Apr '23

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74100 ) Change subject: mb/google/myst: Add smihandler ...................................................................... mb/google/myst: Add smihandler Add SMI handler code for Myst platform. BUG=b:275858191 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74100 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/smihandler.c 2 files changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc index 9fb63f5..ba09623 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c + +smm-y += smihandler.c diff --git a/src/mainboard/google/myst/variants/baseboard/smihandler.c b/src/mainboard/google/myst/variants/baseboard/smihandler.c new file mode 100644 index 0000000..7d439d5 --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/smihandler.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> +#include <variant/ec.h> + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S0IX_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1 Gerrit-Change-Number: 74100 Gerrit-PatchSet: 23 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Enable chromeOS EC
by Raul Rangel (Code Review) 11 Apr '23

11 Apr '23

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74099 ) Change subject: mb/google/myst: Enable chromeOS EC ...................................................................... mb/google/myst: Enable chromeOS EC BUG=b:270624655 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74099 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/Makefile.inc M src/mainboard/google/myst/chromeos.c M src/mainboard/google/myst/dsdt.asl A src/mainboard/google/myst/ec.c M src/mainboard/google/myst/mainboard.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb A src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h 8 files changed, 150 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index 6537cce..59eabe4 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI select MAINBOARD_HAS_CHROMEOS select SOC_AMD_PHOENIX @@ -36,7 +38,8 @@ default "myst" if BOARD_GOOGLE_MYST config VBOOT - select VBOOT_NO_BOARD_SUPPORT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_LID_SWITCH select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc index 9060a73..418ff9e 100644 --- a/src/mainboard/google/myst/Makefile.inc +++ b/src/mainboard/google/myst/Makefile.inc @@ -4,6 +4,7 @@ romstage-y += port_descriptors.c +ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c index 9f4a3cb..e488e81 100644 --- a/src/mainboard/google/myst/chromeos.c +++ b/src/mainboard/google/myst/chromeos.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/gpio.h> +#include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> +void fill_lb_gpios(struct lb_gpios *gpios) {} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/myst/dsdt.asl b/src/mainboard/google/myst/dsdt.asl index 80a9c1f..9c7dc36 100644 --- a/src/mainboard/google/myst/dsdt.asl +++ b/src/mainboard/google/myst/dsdt.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <variant/ec.h> DefinitionBlock ( "dsdt.aml", @@ -13,4 +14,16 @@ { #include <acpi/dsdt_top.asl> #include <soc.asl> + + Name (LIDS, 0) + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } + } diff --git a/src/mainboard/google/myst/ec.c b/src/mainboard/google/myst/ec.c new file mode 100644 index 0000000..c369f14 --- /dev/null +++ b/src/mainboard/google/myst/ec.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <ec/google/chromeec/ec.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index 56329ee..bdd4c76 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <console/console.h> #include <device/device.h> +#include <variant/ec.h> static const struct fch_irq_routing fch_irq_map[] = { { 0, 0x00, 0x00 }, @@ -30,6 +31,7 @@ static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); + mainboard_ec_init(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 164a47a..ef41b0d 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -1,4 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/phoenix - device domain 0 on end # domain + device domain 0 on + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 alias chrome_ec on end + end + end + end # domain end # chip soc/amd/phoenix diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..c6ab30f --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> +#include <gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BODY_DETECT_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid, power button or mode change event */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Set GPI for SCI */ +#define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */ + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GEVENT_13 /* AGPIO 17 -> GPE 13 */ + +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1} + +/* Enable EC sync interrupt */ +#define EC_ENABLE_SYNC_IRQ_GPIO + +/* EC sync irq */ +#define EC_SYNC_IRQ GPIO_90 + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif /* __MAINBOARD_EC_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Gerrit-Change-Number: 74099 Gerrit-PatchSet: 20 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel: Introduce ioapic_get_sci_pin()
by Kyösti Mälkki (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Werner Zeh. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74326 ) Change subject: soc/intel: Introduce ioapic_get_sci_pin() ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Werner, APL seems the only with !ACPI_HAVE_PCAT_8259. Do siemens/mc_aplX use SCI_IRQ 9? -- To view, visit https://review.coreboot.org/c/coreboot/+/74326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Gerrit-Change-Number: 74326 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 20:30:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable variants for Myst
by Raul Rangel (Code Review) 11 Apr '23

11 Apr '23

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74098 ) Change subject: mb/google/myst: Enable variants for Myst ...................................................................... mb/google/myst: Enable variants for Myst BUG=b:270618107 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/Makefile.inc M src/mainboard/google/myst/mainboard.c A src/mainboard/google/myst/variants/myst/include/variant/ec.h A src/mainboard/google/myst/variants/myst/overridetree.cb 5 files changed, 36 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index b9e87fb..6537cce 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -27,6 +27,14 @@ config MAINBOARD_PART_NUMBER default "Myst" if BOARD_GOOGLE_MYST +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VARIANT_DIR + string + default "myst" if BOARD_GOOGLE_MYST + config VBOOT select VBOOT_NO_BOARD_SUPPORT select VBOOT_SEPARATE_VERSTAGE diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc index 5bd6aca..9060a73 100644 --- a/src/mainboard/google/myst/Makefile.inc +++ b/src/mainboard/google/myst/Makefile.inc @@ -9,5 +9,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard +subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index bba9fc2..56329ee 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -2,6 +2,7 @@ #include <amdblocks/amd_pci_util.h> #include <baseboard/variants.h> +#include <console/console.h> #include <device/device.h> static const struct fch_irq_routing fch_irq_map[] = { @@ -33,7 +34,7 @@ static void mainboard_enable(struct device *dev) { - /* TODO(b/270618107): Enable mainboard */ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/myst/variants/myst/include/variant/ec.h b/src/mainboard/google/myst/variants/myst/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/myst/variants/myst/overridetree.cb b/src/mainboard/google/myst/variants/myst/overridetree.cb new file mode 100644 index 0000000..164a47a --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/overridetree.cb @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/phoenix + device domain 0 on end # domain +end # chip soc/amd/phoenix -- To view, visit https://review.coreboot.org/c/coreboot/+/74098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7 Gerrit-Change-Number: 74098 Gerrit-PatchSet: 18 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel: Introduce ioapic_get_sci_pin()
by Kyösti Mälkki (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74326 ) Change subject: soc/intel: Introduce ioapic_get_sci_pin() ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/baytrail/acpi.c: https://review.coreboot.org/c/coreboot/+/74326/comment/678c8302_69d2f63e PS1, Line 299: current += acpi_create_madt_irqoverride(irqovr, 0, irq, gsi, flags); > In the case !ACPI_HAVE_PCAT_8259, assert irq==gsi since no redirection is desired ? Newly introduced acpi_create_madt_sci_override() should avoid the redirection now. -- To view, visit https://review.coreboot.org/c/coreboot/+/74326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Gerrit-Change-Number: 74326 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 20:20:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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