coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Paul Fagerburg (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Kapil Porwal. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 18:28:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/mtl: Add meteorlake B0 stepping CPU ID
by Musse Abdullahi (Code Review) 11 Apr '23

11 Apr '23

Musse Abdullahi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74300 ) Change subject: soc/intel/mtl: Add meteorlake B0 stepping CPU ID ...................................................................... soc/intel/mtl: Add meteorlake B0 stepping CPU ID Signed-off-by: Musse Abdullahi <musse.abdullahi(a)intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/meteorlake/bootblock/report_platform.c 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/74300/1 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 7caafd5..2d64c5f 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -71,6 +71,7 @@ #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 +#define CPUID_METEORLAKE_B0 0xa06a2 #define CPUID_RAPTORLAKE_P_J0 0xb06a2 #define CPUID_RAPTORLAKE_P_Q0 0xb06a3 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 6689047..7466ff6 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -34,6 +34,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index a5d32f3..3e8bc56 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -19,6 +19,7 @@ } cpu_table[] = { { CPUID_METEORLAKE_A0_1, "MeteorLake A0" }, { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, + { CPUID_METEORLAKE_B0, "MeteorLake B0" }, }; static struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/74300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Gerrit-Change-Number: 74300 Gerrit-PatchSet: 1 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common: Identify FSP HOB type GUIDs
by Martin L Roth (Code Review) 11 Apr '23

11 Apr '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74344 ) Change subject: soc/amd/common: Identify FSP HOB type GUIDs ...................................................................... soc/amd/common: Identify FSP HOB type GUIDs This identifies GUIDs used in the AMD FSP so they don't display as "Unknown GUID". Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I3e0b4c3e3c7b6271ac64f9296c8a3f46d28e244d --- M src/soc/amd/common/fsp/Makefile.inc A src/soc/amd/common/fsp/hob_display.c 2 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/74344/1 diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc index ab9a7ab..2848830 100644 --- a/src/soc/amd/common/fsp/Makefile.inc +++ b/src/soc/amd/common/fsp/Makefile.inc @@ -2,7 +2,10 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += fsp_reset.c romstage-y += fsp_validate.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c + ramstage-y += fsp_reset.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_CCX_CPPC_HOB) += fsp_ccx_cppc_hob.c ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_DMI_TABLES) += dmi.c diff --git a/src/soc/amd/common/fsp/hob_display.c b/src/soc/amd/common/fsp/hob_display.c new file mode 100644 index 0000000..dac2f25 --- /dev/null +++ b/src/soc/amd/common/fsp/hob_display.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> + +static const EFI_GUID fsp_hob_gnb_pcie_info_guid = { 0x03eb1d90, 0xce14, 0x40d8, + {0xa6, 0xba, 0x10, 0x3a, 0x8d, 0x7b, 0xd3, 0x2d} }; +static const EFI_GUID fsp_hob_mem_info_guid = { 0x1bce3d14, 0xa5fe, 0x4a0b, + {0x9a, 0x8d, 0x69, 0xca, 0x5d, 0x98, 0x38, 0xd3} }; +static const EFI_GUID fsp_hob_fch_reset_data_guid = { 0x26ab8e31, 0x6c47, 0x480a, + {0xa0, 0x39, 0x1e, 0x04, 0x3f, 0xa7, 0x93, 0xcd} }; +static const EFI_GUID fsp_hob_misc_data_guid = { 0x27f7d972, 0x318f, 0x4665, + {0x8a, 0x99, 0xf4, 0x4c, 0x04, 0x4b, 0x49, 0x08} }; +static const EFI_GUID fsp_hob_ccx_cppc_export_guid = { 0x3060c5ec, 0x7399, 0x432d, + {0xbc, 0x97, 0xbf, 0x95, 0xe4, 0x3d, 0x53, 0x0c} }; +static const EFI_GUID fsp_hob_amd_apob_guid = { 0x30b174f3, 0x7712, 0x4cca, + {0xbd, 0x13, 0xd0, 0xb8, 0xa8, 0x80, 0x19, 0x97} }; +static const EFI_GUID fsp_hob_ext_fw_perf_guid = { 0x3b387bfd, 0x7abc, 0x4cf2, + {0xa0, 0xca, 0xb6, 0xa1, 0x6c, 0x1b, 0x1b, 0x25} }; +static const EFI_GUID fsp_hob_dmi_guid = { 0x4118fc0e, 0x353d, 0x4726, + {0x97, 0xc0, 0x53, 0xcd, 0x92, 0xb6, 0x49, 0x25} }; +static const EFI_GUID fsp_hob_cpu_init_mp_guid = { 0x58eb6a19, 0x3699, 0x4c68, + {0xa8, 0x36, 0xda, 0xcd, 0x8e, 0xdc, 0xad, 0x4a} }; +static const EFI_GUID fsp_hob_tseg_guid = { 0x5fc7897a, 0x5aff, 0x4c61, + {0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c} }; +static const EFI_GUID fsp_hob_pcie_remap_guid = { 0x6d5cd69d, 0xfb24, 0x4461, + {0xaa, 0x32, 0x8e, 0xe1, 0xb3, 0x03, 0x31, 0x9c} }; +static const EFI_GUID fsp_hob_gnb_sys_info_guid = { 0x89d85219, 0x2ca1, 0x42de, + {0x99, 0x32, 0x74, 0x88, 0xdf, 0x4f, 0x5f, 0x83} }; +static const EFI_GUID fsp_hob_pcd_peim_guid = { 0x9b3ada4f, 0xae56, 0x4c24, + {0x8d, 0xea, 0xf0, 0x3b, 0x75, 0x58, 0xae, 0x50} }; +static const EFI_GUID fsp_hob_sec_plat_info_guid = { 0x9e9f374b, 0x8f16, 0x4230, + {0x98, 0x24, 0x58, 0x46, 0xee, 0x76, 0x6a, 0x97} }; +static const EFI_GUID fsp_hob_gnb_pei_gop_guid = { 0xa90f3dfd, 0xdb05, 0x4e73, + {0x86, 0x75, 0x0d, 0xd1, 0x0f, 0x66, 0x9e, 0x0f} }; +static const EFI_GUID fsp_hob_error_log_guid = { 0xace4c26a, 0x4a31, 0x4861, + {0x8e, 0xf9, 0xda, 0xd0, 0x7c, 0xfd, 0x39, 0x1f} }; +static const EFI_GUID fsp_hob_serial_console_guid = { 0xbea654e4, 0x4770, 0x4b8d, + {0x95, 0x24, 0xc0, 0xf0, 0xdb, 0xe9, 0xe9, 0x86} }; +static const EFI_GUID fsp_hob_ucode_patch_guid = { 0xd178f11d, 0x8716, 0x418e, + {0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43} }; +static const EFI_GUID fsp_hob_heap_guid = { 0xd97d161a, 0x16cd, 0x4ada, + {0xb9, 0xf6, 0xae, 0xc3, 0xf9, 0xfc, 0xcc, 0x2c} }; +static const EFI_GUID fsp_hob_gfx_dev_info_guid = { 0xe5cb2ac9, 0xd35d, 0x4430, + {0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7} }; +static const EFI_GUID fsp_hob_pcd_data_base_guid = { 0xea296d92, 0x0b69, 0x423c, + {0x8c, 0x28, 0x33, 0xb4, 0xe0, 0xa9, 0x12, 0x68} }; +static const EFI_GUID fsp_hob_mmio_base_guid = { 0xfabe7090, 0x71cc, 0x4266, + {0x9b, 0x4f, 0x33, 0x0c, 0x0b, 0x32, 0x94, 0xf6} }; +static const EFI_GUID fsp_hob_data_guid = { 0xF2784616, 0xB9BF, 0x4E1E, + {0x99, 0xE0, 0x96, 0x26, 0xDA, 0x7E, 0xA5, 0xF5 }}; +static const EFI_GUID fsp_hob_core_info_guid = { 0x0cdfa7da, 0x0d0b, 0x41f0, + {0xb9, 0x8b, 0x0f, 0x63, 0x59, 0xc0, 0x85, 0x7f}}; + + +struct guid_name_map { + const void *guid; + const char *name; +}; + +static const struct guid_name_map guid_names[] = { + {&fsp_hob_gnb_pcie_info_guid, "FSP_HOB_GNB_PCIE_INFO_GUID" }, + {&fsp_hob_mem_info_guid, "FSP_HOB_MEM_INFO_GUID"}, + {&fsp_hob_fch_reset_data_guid, "FSP_HOB_FCH_RESET_DATA_GUID"}, + {&fsp_hob_misc_data_guid, "FSP_HOB_MISC_DATA_GUID"}, + {&fsp_hob_ccx_cppc_export_guid, "FSP_HOB_CCX_CPPC_EXPORT_GUID"}, + {&fsp_hob_amd_apob_guid, "FSP_HOB_AMD_APOB_GUID"}, + {&fsp_hob_ext_fw_perf_guid, "FSP_HOB_EXT_FW_PERF_GUID"}, + {&fsp_hob_dmi_guid, "FSP_HOB_DMI_GUID"}, + {&fsp_hob_cpu_init_mp_guid, "FSP_HOB_CPU_INIT_MP_GUID"}, + {&fsp_hob_tseg_guid, "FSP_HOB_TSEG_GUID"}, + {&fsp_hob_pcie_remap_guid, "FSP_HOB_PCIE_REMAP_GUID"}, + {&fsp_hob_gnb_sys_info_guid, "FSP_HOB_GNB_SYS_INFO_GUID"}, + {&fsp_hob_pcd_peim_guid, "FSP_HOB_PCD_PEIM_GUID"}, + {&fsp_hob_sec_plat_info_guid, "FSP_HOB_SEC_PLAT_INFO_GUID"}, + {&fsp_hob_gnb_pei_gop_guid, "FSP_HOB_GNB_PEI_GOP_GUID"}, + {&fsp_hob_error_log_guid, "FSP_HOB_ERROR_LOG_GUID"}, + {&fsp_hob_serial_console_guid, "FSP_HOB_SERIAL_CONSOLE_GUID"}, + {&fsp_hob_ucode_patch_guid, "FSP_HOB_UCODE_PATCH_GUID"}, + {&fsp_hob_heap_guid, "FSP_HOB_HEAP_GUID"}, + {&fsp_hob_gfx_dev_info_guid, "FSP_HOB_GFX_DEV_INFO_GUID"}, + {&fsp_hob_pcd_data_base_guid, "FSP_HOB_PCD_DATA_BASE_GUID"}, + {&fsp_hob_mmio_base_guid, "FSP_HOB_MMIO_BASE_GUID"}, + {&fsp_hob_data_guid, "AMD_FSP_DATA_HOB_GUID"}, + {&fsp_hob_core_info_guid, "FSP_HOB_CORE_INFO_GUID"}, +}; + +const char *soc_get_guid_name(const uint8_t *guid) +{ + size_t index; + + /* Compare the GUID values in this module */ + for (index = 0; index < ARRAY_SIZE(guid_names); index++) + if (fsp_guid_compare(guid, guid_names[index].guid)) + return guid_names[index].name; + + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e0b4c3e3c7b6271ac64f9296c8a3f46d28e244d Gerrit-Change-Number: 74344 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Mark Hasemeyer (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Mark Hasemeyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 33: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 33 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 17:36:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Tim Van Patten (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 33: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 33 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 17:30:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add ACPI configuration for USB ports
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Paul Menzel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74106 ) Change subject: mb/google/myst: Add ACPI configuration for USB ports ...................................................................... Patch Set 26: (4 comments) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74106/comment/f063565e_b8403249 PS25, Line 49: register "desc" = ""USB2 Type-A Port A0 (MLB)"" > This is an internal port for UCAM. Done https://review.coreboot.org/c/coreboot/+/74106/comment/82fdc151_342bcbf0 PS25, Line 54: register "desc" = ""User-Facing Camera"" > This is used by WCAM Done https://review.coreboot.org/c/coreboot/+/74106/comment/e79be588_59bb6ee8 PS25, Line 59: Facing > This is used by BT. Done https://review.coreboot.org/c/coreboot/+/74106/comment/119e4bfc_ffff8521 PS25, Line 69: chip drivers/usb/acpi : register "desc" = ""USB3 Type-A Port A0 (DB)"" : register "type" = "UPC_TYPE_USB3_A" : register "group" = "ACPI_PLD_GROUP(2, 1)" : device ref usb3_port5 on end : end : chip drivers/usb/acpi : register "desc" = ""USB2 Type-A Port A0 (MLB)"" : register "type" = "UPC_TYPE_USB3_A" : register "group" = "ACPI_PLD_GROUP(2, 1)" : device ref usb2_port5 on end : end : chip drivers/usb/acpi : register "desc" = ""Bluetooth"" : register "type" = "UPC_TYPE_INTERNAL" : register "has_power_resource" = "true" : register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_154)" : register "enable_delay_ms" = "500" : register "enable_off_delay_ms" = "200" : register "use_gpio_for_status" = "true" : device ref usb2_port6 on end : end > Nothing in this XHCI seems used based on the schematics. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Gerrit-Change-Number: 74106 Gerrit-PatchSet: 26 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 17:29:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 33: (1 comment) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74112/comment/4b1d2fc6_93a27328 PS31, Line 12: .start_logical_lane = 13, : .end_logical_lane = 13, > The actual schematic shows lane 13, not sure why the block diagram shows lane 12. […] Block diagram has been updated, it should be 13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 33 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 17:26:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Configure WLAN
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74113 to look at the new patch set (#35). Change subject: mb/google/myst: Configure WLAN ...................................................................... mb/google/myst: Configure WLAN Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mapping derived from myst schematic. BUG=b:275965982 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/bootblock.c A src/mainboard/google/myst/romstage.c M src/mainboard/google/myst/variants/baseboard/Makefile.inc M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 7 files changed, 107 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74113/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/74113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b Gerrit-Change-Number: 74113 Gerrit-PatchSet: 35 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74112 to look at the new patch set (#33). Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... mb/google/myst: Enable PCIe devices in devicetree Ensure that DXIO descriptors are updated using info from AMD and Myst board schematics. BUG=b:275960920,b:276744321 TEST=builds Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 3 files changed, 119 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74112/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 33 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Add ACPI configuration for USB ports
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Paul Menzel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74106 to look at the new patch set (#26). Change subject: mb/google/myst: Add ACPI configuration for USB ports ...................................................................... mb/google/myst: Add ACPI configuration for USB ports The USB port configuration was derived from the PPR and schematics. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras (World/User facing) 1 Bluetooth transceiver 1 WWAN BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 143 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74106/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/74106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Gerrit-Change-Number: 74106 Gerrit-PatchSet: 26 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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