coreboot-gerrit April 2023

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[M] Change in coreboot[master]: soc/intel/: Store ISH firmware version into cbmem table
by Dinesh Gehlot (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74208 to look at the new patch set (#12). Change subject: soc/intel/: Store ISH firmware version into cbmem table ...................................................................... soc/intel/: Store ISH firmware version into cbmem table The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 Test=The current and old cse and ish versions are verified on the nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 --- M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 84 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/74208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Gerrit-Change-Number: 74208 Gerrit-PatchSet: 12 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69950 ) Change subject: soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden ...................................................................... soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden Set the P2SB device as hidden as FSP-S is hiding the PCI configuration space from coreboot on Alder Lake systems. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69950 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/chipset_pch_s.cb 2 files changed, 19 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index b9abe06..ed8ae04 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -248,7 +248,7 @@ device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index a2337d6..077cdb6 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -242,7 +242,7 @@ device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end -- To view, visit https://review.coreboot.org/c/coreboot/+/69950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d Gerrit-Change-Number: 69950 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up P2SB PCI ops
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69949 ) Change subject: soc/intel/alderlake: Hook up P2SB PCI ops ...................................................................... soc/intel/alderlake: Hook up P2SB PCI ops P2SB device is being hidden from coreboot by FSP-S. This breaks the resource allocator which does not report P2SB BAR via intel common block P2SB driver. Hook up the common block P2SB driver ops to soc_enable function so that the resources will be reported. The P2SB device must be set as hidden in the devicetree. This fixes the silent resource allocation conflicts on machines with devices having big BARs which accidentally overlapped P2SB BAR. TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big BARs and see resource conflicts no longer occur. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7c59441268676a8aab075abbc036e651b9426057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69949 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/p2sb.h 2 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 25b412e..7cdeb7c 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -16,6 +16,7 @@ #include <soc/hsphy.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> +#include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcie.h> #include <soc/ramstage.h> @@ -244,6 +245,7 @@ static void soc_enable(struct device *dev) { + struct device_operations *soc_p2sb_ops = (struct device_operations *)&p2sb_ops; /* * Set the operations if it is a special bus type or a hidden PCI * device. @@ -255,6 +257,9 @@ else if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCH_DEVFN_PMC) dev->ops = &pmc_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCH_DEVFN_P2SB) + dev->ops = soc_p2sb_ops; else if (dev->path.type == DEVICE_PATH_GPIO) block_gpio_enable(dev); } diff --git a/src/soc/intel/alderlake/include/soc/p2sb.h b/src/soc/intel/alderlake/include/soc/p2sb.h index 2726851..367ace2 100644 --- a/src/soc/intel/alderlake/include/soc/p2sb.h +++ b/src/soc/intel/alderlake/include/soc/p2sb.h @@ -14,4 +14,6 @@ #define PCH_P2SB_EPMASK0 0x220 +extern const struct device_operations p2sb_ops; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c59441268676a8aab075abbc036e651b9426057 Gerrit-Change-Number: 69949 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up P2SB PCI ops
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli, Michał Żygowski, Michał Kopeć, Krystian Hebel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69949 ) Change subject: soc/intel/alderlake: Hook up P2SB PCI ops ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/69949/comment/d3134f5b_540200ce PS5, Line 252: if (dev->path.type == DEVICE_PATH_DOMAIN) : dev->ops = &pci_domain_ops; : else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) : dev->ops = &cpu_bus_ops; : else if (dev->path.type == DEVICE_PATH_PCI && : dev->path.pci.devfn == PCH_DEVFN_PMC) : dev->ops = &pmc_ops; : else if (dev->path.type == DEVICE_PATH_PCI && : dev->path.pci.devfn == PCH_DEVFN_P2SB) : dev->ops = soc_p2sb_ops; not directly related to this patch, but i'd recommend adding the device ops to the chipset devicetree file as ops instead of adding it during runtime -- To view, visit https://review.coreboot.org/c/coreboot/+/69949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c59441268676a8aab075abbc036e651b9426057 Gerrit-Change-Number: 69949 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:34:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Add DTT thermal settings for thermal control
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71166 ) Change subject: mb/google/rex: Add DTT thermal settings for thermal control ...................................................................... mb/google/rex: Add DTT thermal settings for thermal control Add DTT thermal settings for thermal control provided by thermal team for rex0 board BRANCH=None BUG=b:262498724, b:270664854 TEST=Built and verified thermal entries in ACPI SSDT on Rex board Change-Id: I00dd97b759c8c68edaeeb4d64422b83c5e86981d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71166 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 141 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 282c3da..17e4c3e 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -133,6 +133,126 @@ device domain 0 on device ref dtt on chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""wwan"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 50), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 57000, + .max_power = 57000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + device generic 0 alias dptf_policy on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/71166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00dd97b759c8c68edaeeb4d64422b83c5e86981d Gerrit-Change-Number: 71166 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Enable internal graphics
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Paul Menzel, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74104 ) Change subject: mb/google/myst: Enable internal graphics ...................................................................... Patch Set 25: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74104/comment/817dbb23_83aa41b8 PS25, Line 11: device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A : device ref gfx on end # Internal GPU (GFX) : end > Please move this inside domain 0 in this CL itself. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Gerrit-Change-Number: 74104 Gerrit-PatchSet: 25 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:29:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Lower log level for TDP value to DEBUG
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74271 ) Change subject: soc/amd/mendocino: Lower log level for TDP value to DEBUG ...................................................................... soc/amd/mendocino: Lower log level for TDP value to DEBUG Printing the value of a variable is not informative for a normal user, so decrease the value from BIOS_INFO to BIOS_DEBUG. Fixes: b9caac74a320 ("soc/amd/mendocino: Reinterpret smu_power_and_thm_limit") Change-Id: I22f6293fd47633dfdbdae37b7257f47a5a4bb29c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74271 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> --- M src/soc/amd/mendocino/fsp_misc_data_hob.c 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Van Patten: Looks good to me, approved diff --git a/src/soc/amd/mendocino/fsp_misc_data_hob.c b/src/soc/amd/mendocino/fsp_misc_data_hob.c index 3b51fd8..ed35800 100644 --- a/src/soc/amd/mendocino/fsp_misc_data_hob.c +++ b/src/soc/amd/mendocino/fsp_misc_data_hob.c @@ -48,7 +48,7 @@ * we're interested in. For example: 0xF0000 (15W), 0x60000 (6W). Re-interpret * the value so the caller just sees the TDP. */ - printk(BIOS_INFO, "fsp_misc_data->smu_power_and_thm_limit = 0x%08X\n", + printk(BIOS_DEBUG, "fsp_misc_data->smu_power_and_thm_limit = 0x%08X\n", fsp_misc_data->smu_power_and_thm_limit); *tdp = fsp_misc_data->smu_power_and_thm_limit >> 16; -- To view, visit https://review.coreboot.org/c/coreboot/+/74271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22f6293fd47633dfdbdae37b7257f47a5a4bb29c Gerrit-Change-Number: 74271 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/xeon_sp/acpi: Fix _OSC method
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74231 ) Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method ...................................................................... soc/intel/xeon_sp/acpi: Fix _OSC method Fix a couple of bugs in the _OSC method for handling "PCI Host Bridge Device" on Xeon-SP. - Drop the Sleep. The code doesn't write to hardware at all, so there's no need to sleep here. - Make sure that the number of DWORD passed in Arg2 is at least 3. The existing check was useless as it would not create the DWordField, but then use it anyways. - Add check for CXL 2 device method calls which provide a 5 DWORD long buffer to prevent buffer overflows when invoking the "PCI Host Bridge Device" method. Test: Boot on Archer City and confirm that no ACPI errors are reported for _OSC. Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74231 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> --- M src/soc/intel/xeon_sp/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl 3 files changed, 58 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index 91a5c6c..e5e6bdc 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -27,17 +27,18 @@ CreateDWordField (Arg3, 0x00, CDW1) \ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ { \ - CreateDWordField (Arg3, 0x04, CDW2) \ - If ((Arg2 > 0x02)) \ + If (Arg2 < 0x03) \ { \ - CreateDWordField (Arg3, 0x08, CDW3) \ + CDW1 |= 0x02 /* Unknown failure */ \ + Return (Arg3) \ } \ + CreateDWordField (Arg3, 0x04, CDW2) \ + CreateDWordField (Arg3, 0x08, CDW3) \ SUPP = CDW2 \ CTRL = CDW3 \ If ((AHPE || ((SUPP & 0x16) != 0x16))) \ { \ CTRL &= 0x1E \ - Sleep (0x03E8) \ } \ /* Never allow SHPC (no SHPC controller in system) */ \ CTRL &= 0x1D \ diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 299247f..3644e87 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -40,24 +40,28 @@ { CreateDWordField (Arg3, 0x00, CDW1) If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */ - || Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) - /* CXL */ + || Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */ { - CreateDWordField (Arg3, 0x04, CDW2) - If (Arg2 > 0x02) + If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */ { - CreateDWordField (Arg3, 0x08, CDW3) - CreateDWordField (Arg3, 0x0C, CDW4) - CreateDWordField (Arg3, 0x10, CDW5) + CDW1 |= 0x02 /* Unknown failure */ + Return (Arg3) } + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 CTRL = CDW3 - SUPC = CDW4 - CTRC = CDW5 + If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */ + { + CreateDWordField (Arg3, 0x0C, CDW4) + CreateDWordField (Arg3, 0x10, CDW5) + SUPC = CDW4 + CTRC = CDW5 + } If (SUPP & 0x16 != 0x16) { CTRL &= 0x1E - Sleep (0x03E8) } /* Never allow SHPC (no SHPC controller in system) */ CTRL &= 0x1D @@ -72,7 +76,10 @@ CDW1 |= 0x10 } CDW3 = CTRL - CDW5 = CTRC + If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */ + { + CDW5 = CTRC + } Return (Arg3) } Else diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index 7988a16..a369b11 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -35,17 +35,19 @@ CreateDWordField (Arg3, 0x00, CDW1) If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) { - CreateDWordField (Arg3, 0x04, CDW2) - If (Arg2 > 0x02) + If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */ { - CreateDWordField (Arg3, 0x08, CDW3) + CDW1 |= 0x02 /* Unknown failure */ + Return (Arg3) } + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 CTRL = CDW3 If (SUPP & 0x16 != 0x16) { CTRL &= 0x1E - Sleep (0x03E8) } /* Never allow SHPC (no SHPC controller in system) */ CTRL &= 0x1D -- To view, visit https://review.coreboot.org/c/coreboot/+/74231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Gerrit-Change-Number: 74231 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/xeon_sp/acpi: Fix _OSC method
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Ziang Wang, Christian Walter, Maximilian Brune, Arthur Heymans, Tim Chu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74231 ) Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: would be good if you could split patches that do multiple things into multiple patches that do one thing in the future. i don't expect this to be much of a problem in this specific case, so i'll submit the patch anyway -- To view, visit https://review.coreboot.org/c/coreboot/+/74231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Gerrit-Change-Number: 74231 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:27:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Expose SKU and board ID to Chrome OS
by Jon Murphy (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Eric Lai, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74283 to look at the new patch set (#8). Change subject: mb/google/myst: Expose SKU and board ID to Chrome OS ...................................................................... mb/google/myst: Expose SKU and board ID to Chrome OS Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to provide common routine for reading skudid and boardid from Chrome EC. BUG=b:277293398 TEST=builds Change-Id: I8e42ba23dada9771f335df34275e44e51d645596 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/Kconfig 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74283/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/74283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e42ba23dada9771f335df34275e44e51d645596 Gerrit-Change-Number: 74283 Gerrit-PatchSet: 8 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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