coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/myst: Enable internal graphics
by Karthik Ramasubramanian (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Paul Menzel, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74104 ) Change subject: mb/google/myst: Enable internal graphics ...................................................................... Patch Set 25: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Gerrit-Change-Number: 74104 Gerrit-PatchSet: 25 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:13:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable internal graphics
by Karthik Ramasubramanian (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Paul Menzel, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74104 ) Change subject: mb/google/myst: Enable internal graphics ...................................................................... Patch Set 25: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74104/comment/8fd0a256_b3859d6f PS25, Line 11: device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A : device ref gfx on end # Internal GPU (GFX) : end Please move this inside domain 0 in this CL itself. -- To view, visit https://review.coreboot.org/c/coreboot/+/74104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Gerrit-Change-Number: 74104 Gerrit-PatchSet: 25 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:12:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: amdfwtool: Add --fsp-version option
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Paul Menzel, Arthur Heymans, Grzegorz Bernacki, Fred Reitberger, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74266 ) Change subject: amdfwtool: Add --fsp-version option ...................................................................... Patch Set 1: Code-Review-1 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/74266/comment/c61951b6_49698712 PS1, Line 214: FSP blobs > > > Grzegorz, FSP might be ambiguous as it came originally from Intel for Intel platforms. […] I agree with Arthur that this doesn't belong in amdfwtool -- To view, visit https://review.coreboot.org/c/coreboot/+/74266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Gerrit-Change-Number: 74266 Gerrit-PatchSet: 1 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:10:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Grzegorz Bernacki Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/: Implement an API to get ISH version
by Dinesh Gehlot (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Paul Menzel. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74209 ) Change subject: soc/intel/: Implement an API to get ISH version ...................................................................... Patch Set 6: (2 comments) This change is ready for review. File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/74209/comment/7b222aa0_2d81b82f PS5, Line 544: ROMSTAGE > I think it’s spelled romstage. Ack https://review.coreboot.org/c/coreboot/+/74209/comment/a150cca7_b6329623 PS5, Line 547: if the latest ISH version is not updated in the CBMEM table > Sorry I do not understand, what is supposed to be updated. The API does not update anything, but it provides the user with the current ISH version. It is possible that the stored ISH version is outdated, in which case the API will return false to indicate failure. -- To view, visit https://review.coreboot.org/c/coreboot/+/74209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8 Gerrit-Change-Number: 74209 Gerrit-PatchSet: 6 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:09:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable USB controllers
by Karthik Ramasubramanian (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74105 ) Change subject: mb/google/myst: Enable USB controllers ...................................................................... Patch Set 25: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74105/comment/e87b11fb_cc041801 PS25, Line 14: device ref xhci_1 on end > Done Not sure if it is done. I still see configuration only for xhci controllers under gpp_bridge_a. -- To view, visit https://review.coreboot.org/c/coreboot/+/74105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8 Gerrit-Change-Number: 74105 Gerrit-PatchSet: 25 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:08:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/: Store ISH firmware version into cbmem table
by Dinesh Gehlot (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74208 to look at the new patch set (#11). Change subject: soc/intel/: Store ISH firmware version into cbmem table ...................................................................... soc/intel/: Store ISH firmware version into cbmem table The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 Test=The current and old cse and ish versions are verified on the nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 --- M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 88 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/74208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Gerrit-Change-Number: 74208 Gerrit-PatchSet: 11 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Michał Żygowski (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Maciej Pijanowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer, Michal Zygowski. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 19: (8 comments) File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/27287057_eb81584c PS19, Line 543: "GPP_DSW00", "PMC_BATLOW_N", : "GPP_DSW01", "PMC_ACPRESENT", : "GPP_DSW02", "LAN_WAKE_N", : "GPP_DSW03", "PMC_PWRBTN_N", : "GPP_DSW04", "PMC_SLP_S3_N", : "GPP_DSW05", "PMC_SLP_S4_N", : "GPP_DSW06", "PMC_SLP_A_N", : "GPP_DSW07", "n/a", : "GPP_DSW08", "PMC_SUSCLK", : "GPP_DSW09", "PMC_SLP_WLAN_N", : "GPP_DSW10 GPD, not GPP_DSW to keep consistency with other microarchitectures File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/d5f6640f_b1924e00 PS17, Line 15: "ESPI_RESET,_N", > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/210239f1_187ff932 PS17, Line 18: "SMB_ALERT_,N", > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/557e524a_43cdf2cd PS17, Line 148: "GPP_L_BKLTEN", "GPP_L_BKLTEN", : "GPP_L_BKLTCTL", "GPP_L_BKLTCTL", : "GPP_LVDDEN", "GPP_LVDDEN", : "GPP_SYS_PWROK", "GPP_SYS_PWROK", : "GPP_SYS_RESETB", "GPP_SYS_RESETB", : "GPP_MLK_RSTB", "GPP_MLK_RSTB", > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/5fe4aed5_19158be3 PS17, Line 157: GPP_HVCMOS > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/31c1e67a_36c6559c PS17, Line 503: const char *const jasperlake_pch_group_vgpio_padding_names [] ={ > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/f33f0d7e_c6f84b50 PS17, Line 554: "GPD_INPUT3VSEL", "GPD_INPUT3VSEL", : "GPD_SLP_SUSB", "GPD_SLP_SUSB", : "GPD_WAKEB", "GPD_WAKEB", : "GPD_DRAM_RESETB", "GPD_DRAM_RESETB", > Done Ack File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/a8b09fa4_26c6c2ad PS4, Line 496: // Deep Sleep Well group : const char *const jasperlake_pch_group_dsw_names[] = { : "GPP_DSW00", "PMC_BATLOW_N", : "GPP_DSW01", "PMC_ACPRESENT", : "GPP_DSW02", "LAN_WAKE_N", : "GPP_DSW03", "PMC_PWRBTN_N", : "GPP_DSW04", "PMC_SLP_S3_N", : "GPP_DSW05", "PMC_SLP_S4_N", : "GPP_DSW06", "PMC_SLP_A_N", : "GPP_DSW07", "n/a", : "GPP_DSW08", "PMC_SUSCLK", : "GPP_DSW09", "PMC_SLP_WLAN_N", : "GPP_DSW10", "PMC_SLP_S5_N", : }; : > This is actually the GPD group (abbreviation for GPP_DSW). […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 19 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 16:07:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Karol Zmyslowski Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski. Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73934 to look at the new patch set (#19). Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: GW-R86S-P1 Documents: Intel Datasheet: 634545, rev. 001 Document Number: Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 697 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 19 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer
by Felix Held (Code Review) 11 Apr '23

11 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69223 ) Change subject: drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer ...................................................................... drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer Now the CPU topology is filled in struct device during mp_init. Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69223 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 3 files changed, 21 insertions(+), 82 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index d286ee3..a891ba0 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -28,9 +28,6 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { - int apicid; - uint8_t package, core, thread; - if (processor_number >= MIN(get_cpu_count(), CONFIG_MAX_CPUS)) return FSP_NOT_FOUND; @@ -39,14 +36,10 @@ if (!info) return FSP_DEVICE_ERROR; + struct device *dev = info->cpu; + if (processor_info_buffer == NULL) return FSP_INVALID_PARAMETER; - apicid = info->cpu->path.apic.apic_id; - - if (apicid < 0) - return FSP_DEVICE_ERROR; - - processor_info_buffer->ProcessorId = apicid; processor_info_buffer->StatusFlag = PROCESSOR_HEALTH_STATUS_BIT | PROCESSOR_ENABLED_BIT; @@ -54,12 +47,10 @@ if (processor_number == BSP_CPU_SLOT) processor_info_buffer->StatusFlag |= PROCESSOR_AS_BSP_BIT; - /* Fill EFI_CPU_PHYSICAL_LOCATION structure information */ - get_cpu_topology_from_apicid(apicid, &package, &core, &thread); - - processor_info_buffer->Location.Package = package; - processor_info_buffer->Location.Core = core; - processor_info_buffer->Location.Thread = thread; + processor_info_buffer->ProcessorId = dev->path.apic.apic_id; + processor_info_buffer->Location.Package = dev->path.apic.package_id; + processor_info_buffer->Location.Core = dev->path.apic.core_id; + processor_info_buffer->Location.Thread = dev->path.apic.thread_id; return FSP_SUCCESS; } diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 3f0ee67..c317e05 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -15,23 +15,6 @@ #include <soc/soc_chip.h> #include <types.h> -#define CPUID_EXTENDED_CPU_TOPOLOGY 0x0b -#define LEVEL_TYPE_CORE 2 -#define LEVEL_TYPE_SMT 1 - -#define CPUID_CPU_TOPOLOGY(x, val) \ - (((val) >> CPUID_CPU_TOPOLOGY_##x##_SHIFT) & CPUID_CPU_TOPOLOGY_##x##_MASK) - -#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_SHIFT 0x8 -#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_MASK 0xff -#define CPUID_CPU_TOPOLOGY_LEVEL(res) CPUID_CPU_TOPOLOGY(LEVEL_TYPE, (res).ecx) - -#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_SHIFT 0x0 -#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_MASK 0x1f -#define CPUID_CPU_TOPOLOGY_THREAD_BITS(res) CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax) -#define CPUID_CPU_TOPOLOGY_CORE_BITS(res, threadbits) \ - ((CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax)) - threadbits) - #define CPUID_PROCESSOR_FREQUENCY 0X16 #define CPUID_HYBRID_INFORMATION 0x1a @@ -481,52 +464,6 @@ return valid_size; } -/* Get number of bits for core ID and SMT ID */ -static void get_cpu_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - struct cpuid_result cpuid_regs; - int level_num, cpu_id_op = 0; - const uint32_t cpuid_max_func = cpuid_get_max_func(); - - /* Assert if extended CPU topology not supported */ - assert(cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY); - - cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY; - - *core_bits = level_num = 0; - cpuid_regs = cpuid_ext(cpu_id_op, level_num); - - /* Sub-leaf index 0 enumerates SMT level, if not assert */ - assert(CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) == LEVEL_TYPE_SMT); - - *thread_bits = CPUID_CPU_TOPOLOGY_THREAD_BITS(cpuid_regs); - do { - level_num++; - cpuid_regs = cpuid_ext(cpu_id_op, level_num); - if (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) == LEVEL_TYPE_CORE) { - *core_bits = CPUID_CPU_TOPOLOGY_CORE_BITS(cpuid_regs, *thread_bits); - break; - } - /* Stop when level type is invalid i.e 0 */ - } while (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs)); -} - -void get_cpu_topology_from_apicid(uint32_t apicid, uint8_t *package, - uint8_t *core, uint8_t *thread) -{ - - uint32_t core_bits, thread_bits; - - get_cpu_core_thread_bits(&core_bits, &thread_bits); - - if (package) - *package = apicid >> (thread_bits + core_bits); - if (core) - *core = (apicid >> thread_bits) & ((1 << core_bits) - 1); - if (thread) - *thread = apicid & ((1 << thread_bits) - 1); -} - static void sync_core_prmrr(void) { static msr_t msr_base, msr_mask; diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 38c43d8..cbc9e44 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -183,10 +183,6 @@ */ void enable_pm_timer_emulation(void); -/* Derive core, package and thread information from lapic ID */ -void get_cpu_topology_from_apicid(uint32_t apicid, uint8_t *package, - uint8_t *core, uint8_t *thread); - /* * Initialize core PRMRR * -- To view, visit https://review.coreboot.org/c/coreboot/+/69223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755 Gerrit-Change-Number: 69223 Gerrit-PatchSet: 25 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 11 Apr '23

11 Apr '23

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski. Karol Zmyslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 17: (7 comments) Patchset: PS17: I've corrected mentioned mistakes. File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/10baea37_165f208b PS17, Line 15: "ESPI_RESET,_N", > "ESPI_RESET_N" Done https://review.coreboot.org/c/coreboot/+/73934/comment/55eddf72_17d1aafb PS17, Line 18: "SMB_ALERT_,N", > "SMB_ALERT_N" Done https://review.coreboot.org/c/coreboot/+/73934/comment/c4f3df36_30615f0d PS17, Line 148: "GPP_L_BKLTEN", "GPP_L_BKLTEN", : "GPP_L_BKLTCTL", "GPP_L_BKLTCTL", : "GPP_LVDDEN", "GPP_LVDDEN", : "GPP_SYS_PWROK", "GPP_SYS_PWROK", : "GPP_SYS_RESETB", "GPP_SYS_RESETB", : "GPP_MLK_RSTB", "GPP_MLK_RSTB", > These pins should not have GPP_ prefix Done https://review.coreboot.org/c/coreboot/+/73934/comment/d2397e30_992d104a PS17, Line 157: GPP_HVCMOS > Just HVCMOS Done https://review.coreboot.org/c/coreboot/+/73934/comment/e67e6123_9330e54c PS17, Line 503: const char *const jasperlake_pch_group_vgpio_padding_names [] ={ > Just jasperlake_pch_group_vgpio_names and jasperlake_pch_group_vgpio […] Done https://review.coreboot.org/c/coreboot/+/73934/comment/ae16852d_60daadf0 PS17, Line 554: "GPD_INPUT3VSEL", "GPD_INPUT3VSEL", : "GPD_SLP_SUSB", "GPD_SLP_SUSB", : "GPD_WAKEB", "GPD_WAKEB", : "GPD_DRAM_RESETB", "GPD_DRAM_RESETB", > These should not have GPD_ prefix Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 17 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Tue, 11 Apr 2023 15:59:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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