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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72005 )
Change subject: treewide: Remove Intel Quark SoC & Galileo mainboard
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> There are success reports on the mailing list. There are only problems with the payload I believe.
I'll move this to "abandon" status
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Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74087 )
Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
......................................................................
mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
From request, all type C port limit to to Gen1 5GHz.
So enable UPD usb3_port_force_gen1 for Markarth.
BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify the setting will be applied on Markarth.
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: I9314b67a82ad2993c87f0110db5ec927caaa772b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74087
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---
M src/mainboard/google/skyrim/variants/markarth/overridetree.cb
1 file changed, 33 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Amanda Hwang: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
Dtrain Hsu: Looks good to me, approved
Ian Feng: Looks good to me, approved
Patrick Huang: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
Chao Gui: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
index f82fe1b..3939d65 100644
--- a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
@@ -6,6 +6,13 @@
# Remove the sustained_power_limit_mW when STT is enabled
register "sustained_power_limit_mW" = "15000"
+ # set usb3 port force to gen1
+ register "usb3_port_force_gen1" = "{
+ .ports.xhci0_port0 = 1,
+ .ports.xhci1_port0 = 1,
+ .ports.xhci1_port1 = 0,
+ }"
+
device domain 0 on
register "dxio_tx_vboost_enable" = "1"
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74087 )
Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> We can submit this after 24hrs since +2.
The current patchset has been active for 5 days and it has got 4 +2s. So it can be submitted.
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Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73934
to look at the new patch set (#18).
Change subject: util/inteltool: Add support for Jasper Lake
......................................................................
util/inteltool: Add support for Jasper Lake
Tested on: GW-R86S-P1
Documents: Intel Datasheet: 634545, rev. 001
Document Number: Intel Pentium Silver and Intel
Celeron Processor Datasheet, vol. 2 of 2
Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d
Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/jasperlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 697 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/18
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74266 )
Change subject: amdfwtool: Add --fsp-version option
......................................................................
Patch Set 1:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/74266/comment/7cf5fd35_37dce9f8
PS1, Line 214: FSP blobs
> > Grzegorz, FSP might be ambiguous as it came originally from Intel for Intel platforms.
>
> it's not ambiguous, Intel came up with the FSP spec, AMD has implemented it (this will be the 3rd AMD platform doing so). There's nothing platform specific about FSP.
I'm aware that AMD uses FSP for silicon init, but PSP and the parts of it reported here have nothing to do with FSP.
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Change subject: soc/intel/cmn/block: Store ISH firmware version into cbmem table
......................................................................
Patch Set 10:
This change is ready for review.
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Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details
......................................................................
Patch Set 28:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74005/comment/8e90a996_5bd30181
PS27, Line 9: FPT
> Firmware Partition T? or is it PT for partition?
Ack
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74005/comment/9ae7ef69_2143ae6e
PS27, Line 1242: printk(BIOS_ERR, "HECI: Prerequisites not met for fw partition request\n");
> For debugging it might be easier to check each condition separately, and log what condition failed. […]
I agree that is another way to do it. However, I believe that the current clubbed conditions are distinctively identifiable.
https://review.coreboot.org/c/coreboot/+/74005/comment/43fe3fd0_099143ce
PS27, Line 1250: resp->hdr.result
> Is `resp->hdr. […]
No, `resp->hdr.result` is not always set, it depends on the result of the heci_send_receive() operation. If heci_send_receive() succeeds, it returns zero. If it fails, it returns a non-zero value.
https://review.coreboot.org/c/coreboot/+/74005/comment/5ac41c7a_e36c520d
PS27, Line 1260: printk(BIOS_INFO, "CSE: Info request denied, recovery mode or no CSE LITE SKU\n");
> To help debugging an issue, I’d log a dedicated message for each condition.
Ack
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Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Kapil Porwal, Sridhar Siricilla,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74255
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Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info
......................................................................
soc/intel/cmd/block/cse: Add config option for storing fw version info
This patch adds a configuration option,
'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage
of firmware version information in CBMEM memory. This information can be
used to identify the firmware version that is currently installed on the
system. The option depends on the `DRIVERS_INTEL_ISH` option.
BUG=b:273661726
Test=None
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74255/9
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