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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 35:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/6b1078a2_afd5d3e2
PS31, Line 59: GEN3
> Please add a TODO here to enable it: b/277815815
Done
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 35:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/0ecf24de_aa2a2878
PS31, Line 59: GEN3
> GEN4 isn't supported. https://source.chromium. […]
Please add a TODO here to enable it: b/277815815
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Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
......................................................................
Patch Set 4:
(1 comment)
This change is ready for review.
File src/soc/amd/mendocino/Kconfig:
https://review.coreboot.org/c/coreboot/+/74334/comment/7cf4dad9_72dd7eba
PS1, Line 246: SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
> Should this be CBFS_PRELOAD || SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA?
Done
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Hello Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: arch/x86/ioapic: Promote ioapic_get_sci_pin()
......................................................................
arch/x86/ioapic: Promote ioapic_get_sci_pin()
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.
Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/amd/cezanne/acpi.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/glinda/acpi.c
M src/soc/amd/mendocino/acpi.c
M src/soc/amd/phoenix/acpi.c
M src/soc/amd/picasso/acpi.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/intel/baytrail/fadt.c
M src/soc/intel/braswell/fadt.c
M src/soc/intel/broadwell/pch/fadt.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/common/block/acpi/acpi.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/intel/bd82x6x/fadt.c
M src/southbridge/intel/common/pmbase.c
M src/southbridge/intel/i82371eb/fadt.c
M src/southbridge/intel/i82801dx/fadt.c
M src/southbridge/intel/i82801gx/fadt.c
M src/southbridge/intel/i82801ix/fadt.c
M src/southbridge/intel/i82801jx/fadt.c
M src/southbridge/intel/ibexpeak/fadt.c
M src/southbridge/intel/lynxpoint/fadt.c
25 files changed, 50 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/74337/2
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Daniel Rosa Franzini has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 )
Change subject: mb/google/rex: add variant gpio tables for variant creation
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/rex/variants/baseboard/rex/gpio.c:
https://review.coreboot.org/c/coreboot/+/74257/comment/5e8f8e09_bc73c12c
PS3, Line 32: DECLARE_WEAK_CROS_GPIOS(cros_gpios);
> oh can't do that since no _WEAK for that maybe just put empty array.
Will it work with an empty array? Because the symbol need to be weak, if I understand it correctly. The contents of the weak symbol is irrelevant, iirc. Not sure if the weak can be removed here.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73087 )
Change subject: mb/intel/dq67sw: Add LGA1155 microATX mainboard
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Thank you for your reply.
> 2. I think the correct way would be to add this to the Kconfig in a new patch?
Yes, I think that is the way to go.
Regarding 1., it looks like a bug in `cbfstool`. An issue should probably created to track it.
Regarding 3., hopefully somebody can shed some light on it. Gerrit comments are probably not the right forum for such discussions. If nobody responds, this issue should be brought up on the mailing list.
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 35:
(2 comments)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/52a04dba_2eb1bc5d
PS31, Line 59: GEN3
> Done
GEN4 isn't supported. https://source.chromium.org/chromium/chromiumos/third_party/coreboot/+/chro…
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74112/comment/f4f08a67_5be42439
PS31, Line 88: device ref gpp_bridge_2_1 on end # WWAN
: device ref gpp_bridge_2_2 on end # WLAN
: device ref gpp_bridge_2_3 on end # SD
: device ref gpp_bridge_2_4 on end # NVMe
: device ref iommu on end
: device ref lpc_bridge on
: chip ec/google/chromeec
: device pnp 0c09.0 alias chrome_ec on end
: end
: end
> Why was this block removed? Are they added in a different CL now?
Bad rebase
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/myst: Enable tis_plat_irq_status
......................................................................
mb/google/myst: Enable tis_plat_irq_status
This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented,
wasting 20ms to wait on Cr50!
BUG=b:277297687
TEST=builds
Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/variants/baseboard/Makefile.inc
A src/mainboard/google/myst/variants/baseboard/tpm_tis.c
2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/74286/11
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
Change subject: mb/google/myst: Expose SKU and board ID to Chrome OS
......................................................................
mb/google/myst: Expose SKU and board ID to Chrome OS
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.
BUG=b:277293398
TEST=builds
Change-Id: I8e42ba23dada9771f335df34275e44e51d645596
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/Kconfig
1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74283/11
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/myst: Store XHCI PCI resources
......................................................................
mb/google/myst: Store XHCI PCI resources
Implement `smm_mainboard_pci_resource_store_init` to store the
resources for XHCI devices. These stored resources are later used by
the elog code to log XHCI wake events.
BUG=b:277273428
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I608d51f438681ac529323c23cc707845a3d609d1
---
M src/mainboard/google/myst/mainboard.c
1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74281/11
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