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Change subject: soc/mediatek: Add support for regulator VIO18
......................................................................
soc/mediatek: Add support for regulator VIO18
To provide power to MIPI panel STA_HIMAX83102_J02,add support for
regulator VIO18.
BUG=b:272425116
TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie.
Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5
Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com>
---
M src/soc/mediatek/common/include/soc/regulator.h
M src/soc/mediatek/mt8186/include/soc/mt6366.h
M src/soc/mediatek/mt8186/mt6366.c
3 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74341/3
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Change subject: mb/google/corsola: Add detachable Starmie as variant
......................................................................
mb/google/corsola: Add detachable Starmie as variant
The 'Starmie' is a mt8186 detachable reference design that will share
most of Corsola design. For AP firmware, there will be a few changes,
mostly in display (MIPI interface and w/o bridge), so we create it
as a variant in Corsola.
BUG=b:275470328
BRANCH=corsola
TEST=./util/abuild/abuild -t google/corsola -b starmie -a
Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a
Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/corsola/Kconfig
M src/mainboard/google/corsola/Kconfig.name
M src/mainboard/google/corsola/display.c
3 files changed, 33 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74048/9
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/corsola: Add detachable Starmie as variant
......................................................................
mb/google/corsola: Add detachable Starmie as variant
The 'Starmie' is a mt8186 detachable reference design that will share
most of Corsola design. For AP firmware, there will be a few changes,
mostly in display (MIPI interface and w/o bridge), so we create it
as variant in Corsola.
BUG=b:275470328
BRANCH=corsola
TEST=./util/abuild/abuild -t google/corsola -b starmie -a
Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a
Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/corsola/Kconfig
M src/mainboard/google/corsola/Kconfig.name
M src/mainboard/google/corsola/display.c
3 files changed, 33 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74048/8
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73862 )
Change subject: mb/google/skyrim: Hide unused GPP port
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/73862/comment/9b055495_c0ee8fbb
PS1, Line 110: device ref gpp_bridge_3 hidden end
> the chipset devicetree configures the bridges to the different pcie ports as off, but coreboot will […]
For the case maybe set all gpp hidden in chipset.cb?
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Attention is currently required from: Chen-Tsung Hsieh, Tony Huang, Robert Chen, Shou-Chieh Hsu, Shon Wang.
Hello build bot (Jenkins), Tarun Tuli, Chen-Tsung Hsieh, Derek Huang, Robert Chen, Shou-Chieh Hsu, Shon Wang,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/yaviks: Update devicetree based on FW_CONFIG for yavilla
......................................................................
mb/google/nissa/var/yaviks: Update devicetree based on FW_CONFIG for yavilla
Yavilla will leverage yaviks FW build.
It has one additional USB Type-A0 port, support stylus and support WWAN.
Here update devicetree based on FW_CONFIG for yavilla's design.
-Enable USB2 port3 and USB3 port1 for USB2/3 Type-A0
-Enable USB2 port5 and USB3 port3 for WWAN
-Enable pen garage
-Enable rear mipi cam
-Enable Synaptics touchpad
BUG=b:277148122, b:276369170
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/yaviks/include/variant/gpio.h
M src/mainboard/google/brya/variants/yaviks/overridetree.cb
3 files changed, 276 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74261/8
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Change subject: soc/amd/picasso/acpi/northbridge.asl: drop unneeded TOM1&TOM2 externals
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
TOM1 is both used and needed, as per my comments on Stoney
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Change subject: soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 36:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74112/comment/62947c7e_1262bebc
PS36, Line 91: device ref gpp_bridge_2_4 on end # NVMe
@Felix and Martin, same question here https://review.coreboot.org/c/coreboot/+/73862, do we need hidden the rest bridge?
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