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Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
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Patch Set 4: Code-Review+2
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Patch Set 2: Code-Review+2
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Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Hi reviewers,
If you got merge privilege, would you please help to merge this CL. Thank you.
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Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
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Patch Set 5: Code-Review+1
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Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Christian Walter, Shuo Liu, Lean Sheng Tan, Shelly Chang, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
......................................................................
soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
Processor attached memory should not use reserved_ram_from_to and
treat the calculation of gi_mem_size size as 64MB.
By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
this should fix small total memory issue. Before the fix running
command 'free -g -h' under Linux shows the total memory is only 1.4Gi,
after the fix it's showing the expected total memory size 15Gi.
Tested=On AC without attaching CXL memory, the total memory size is
the same as de-selecting SOC_INTEL_HAS_CXL.
On OCP Crater Lake with CXL memory attached, CXL memory can be recognized
in NUMA node 1:
numactl -H
available: 2 nodes (0-1)
node 0 cpus: 0 1 2 3 4 5 6 .. 59
node 0 size: 95854 MB
node 0 free: 93860 MB
node 1 cpus:
node 1 size: 63488 MB
node 1 free: 63488 MB
node distances:
node 0 1
0: 10 14
1: 14 10
Change-Id: I38e9d138fd284620ac616a65f444e943f1774869
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 48 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/74296/5
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Change subject: MAINTAINERS: Update maintainers for MediaTek SoCs and mainboards
......................................................................
MAINTAINERS: Update maintainers for MediaTek SoCs and mainboards
- Add Google MediaTek mainboards
- Update maintainers for MediaTek SoCs and mainboards
Change-Id: Ic3e99b08fe9eb153263470bc6c7a97524e1bf888
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M MAINTAINERS
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Change subject: mb/google/rex: add variant gpio tables for variant creation
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
@YH, let's put the gpio.c and make file to util/mainboard/google/rex0/template/ then you don't need const struct pad_config *variant_gpio_override_table(size_t *num), that's more fit the current design.
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