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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74306
to look at the new patch set (#2).
Change subject: soc/intel/meteorlake: Hook up UPD CnviWifiCore
......................................................................
soc/intel/meteorlake: Hook up UPD CnviWifiCore
Hook the newly created/exposed CnviWifiCore UPD up as a chip driver.
Enable this option by default to maintain the existing behavior.
BUG=b:270985197
TEST=Verified by enabling/disabling the UPD on google/rex
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/chipset.cb
M src/soc/intel/meteorlake/fsp_params.c
3 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74306/2
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74209 )
Change subject: soc/intel/: Implement an API to get ISH version
......................................................................
Patch Set 9:
(3 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74209/comment/252a61b4_41aa42c0
PS9, Line 1277: /*
: * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a
: * default. This is intended for pre-mem usage only where BARs haven't been
: * assigned yet and devices are not enabled.
May I know how this comment is connected with get_ish_version()?
https://review.coreboot.org/c/coreboot/+/74209/comment/7e28ada3_0461c93d
PS9, Line 1282: bool
please prefer enum cb_err.
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/74209/comment/256291ea_c4788da1
PS9, Line 453: bool
please prefer enum cb_err.
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74208 )
Change subject: soc/intel/: Store ISH firmware version into cbmem table
......................................................................
Patch Set 14:
(5 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74208/comment/98e06fad_17c7fe5d
PS14, Line 1278: FSP-M
memory?
https://review.coreboot.org/c/coreboot/+/74208/comment/f2cf1a5b_cbf0335f
PS14, Line 1279: CSE DRAM
DRAM.
CSE needs host memory access for ISH FW patching. Hence DRAM Init is prerequisite to get patched ISH firmware version.
https://review.coreboot.org/c/coreboot/+/74208/comment/27587c62_dcb086d1
PS14, Line 1282: store_ish_version
Can we move this definition to new file?
https://review.coreboot.org/c/coreboot/+/74208/comment/0467ac30_eb6ad64d
PS14, Line 1305: version->ish_partition_info.prev_cse_fw_version.major
: = version->cur_cse_fw_version.major;
: version->ish_partition_info.prev_cse_fw_version.minor
: = version->cur_cse_fw_version.minor;
: version->ish_partition_info.prev_cse_fw_version.hotfix
: = version->cur_cse_fw_version.hotfix;
: version->ish_partition_info.prev_cse_fw_version.build
: = version->cur_cse_fw_version.build;
:
can you define generic function for copying the version from src to destination?
cse_copy_fw_version(struct fw_version *src, struct fw_version *dst)
https://review.coreboot.org/c/coreboot/+/74208/comment/2e7f8f16_00668a4e
PS14, Line 1315: version->ish_partition_info.cur_ish_fw_version.major
: = resp.manifest_data.version.major;
: version->ish_partition_info.cur_ish_fw_version.minor
: = resp.manifest_data.version.minor;
: version->ish_partition_info.cur_ish_fw_version.hotfix
: = resp.manifest_data.version.hotfix;
: version->ish_partition_info.cur_ish_fw_version.build
: = resp.manifest_data.version.build;
You may use generic version copy function (cse_copy_fw_version) for this as described above?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74335 )
Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74335/comment/f5a91275_6de423fd
PS4, Line 10: to achieve the better power savings.
Drop *the*.
https://review.coreboot.org/c/coreboot/+/74335/comment/99f9bb3f_aa55d7cb
PS4, Line 11: * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
Please add a blank line above.
https://review.coreboot.org/c/coreboot/+/74335/comment/f79b4c85_49ee7540
PS4, Line 16:
Please add the exact numbers of power savings to the commit message.
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Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/74221/comment/40e14119_9b0bdf13
PS1, Line 273: acpi_create_dmar_ds_pci
You are not checking if the device is enabled or not. Is this ok?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74229 )
Change subject: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
......................................................................
Patch Set 6:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74229/comment/a9795bed_d219f233
PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB.
> > > The board was apparently added with 8 MB, so why is it too big now? What optimization is done? […]
Thank you for adding that paragraph. It helped me.
https://review.coreboot.org/c/coreboot/+/74229/comment/3f973961_7ed1bda1
PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB.
:
: Changes for chromeos.fmd:
:
: SI_BIOS:
: RW_SECTION_A/B: Reduce to 7MB.
: RW_LEGACY: Reduce to 1MB.
: RW_MISC: Increased to 1MB.
: RW_UNUSED: 3MB (reserved)
: WP_RO: Reduce to 4MB
:
: Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
: SPI Flash.
> > > I am sorry you are feeling this way. […]
A lot of my comments were ignorance and thinking errors on my part. Sorry about that.
File src/mainboard/google/rex/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/74229/comment/4b9e3d4b_3e2834c9
PS1, Line 7: 7M
> > > Changing 7092K to 7M is cosmetic, isn’t it? […]
I am sorry, I miscalculated 7 * 1024 and thought it’s 7092K instead of 7168K. So it’s not a cosmetic change. I am sorry for the noise.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74245 )
Change subject: util/docker/jenkins-node: Clean up package installation
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74245/comment/3f067a47_96e0fe99
PS2, Line 7: Clean up package installation
Maybe:
> Merge Python/Ruby package installation into first install step
https://review.coreboot.org/c/coreboot/+/74245/comment/d8289247_871c1ef9
PS2, Line 11:
It might be the container way, to have an image for each step, so you only need to update smaller layers.
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