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Change subject: mb/amd/mayan: Enable MXM PCIe slot
......................................................................
mb/amd/mayan: Enable MXM PCIe slot
Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b
Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
---
M src/mainboard/amd/mayan/devicetree_phoenix.cb
M src/mainboard/amd/mayan/ec.c
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3 files changed, 41 insertions(+), 6 deletions(-)
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Hello Jason Glenesk, ritul guru, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/amd/mayan: Enable MXM PCIe slot
......................................................................
mb/amd/mayan: Enable MXM PCIe slot
Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b
Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
---
M src/mainboard/amd/mayan/devicetree_phoenix.cb
M src/mainboard/amd/mayan/ec.c
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Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74335/comment/a92a2304_eac8087f
PS4, Line 16:
> This is the first version. We have gotten board.
This is the first version. We have not gotten board yet.
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Johnny Lin has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/73622 )
Change subject: [DEBUG ONLY for weekly check] Add scripts and snapshot.txt to facilitate SPR build
......................................................................
Abandoned
The SPR upstreaming process is looking good and important changes are mostly merged now, abandon this debug change, thanks.
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Change subject: arch/x86/car.ld: Accomodate for FSP spec violation on Xeon-SP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Sapphaire Rapids FSP is not published yet, but the spec version is v2.3.
This issue affecting SPR was reported to Intel on 23.3.2022
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Change subject: soc/intel/meteorlake: Hook up UPD CnviWifiCore
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/meteorlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/74306/comment/2fd3236f_b922d632
PS2, Line 20:
drop one extra line
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Change subject: soc/intel/meteorlake: Hook up UPD CnviWifiCore
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/74306/comment/b8cf32a1_646f203e
PS2, Line 565: s_cfg->CnviWifiCore = config->cnvi_wifi_core;
Do we need assert? Is CnviMode and CnviWifiCore have dependency?
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Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74335/comment/a66f4248_07a0c3cc
PS4, Line 10: to achieve the better power savings.
> Drop *the*.
Done
https://review.coreboot.org/c/coreboot/+/74335/comment/96e763f5_bd1e2b9e
PS4, Line 11: * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
> Please add a blank line above.
Done
https://review.coreboot.org/c/coreboot/+/74335/comment/618a8ee1_0d00be25
PS4, Line 16:
> Please add the exact numbers of power savings to the commit message.
This is the first version. We have gotten board.
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Hello John Su, build bot (Jenkins), Tarun Tuli, Ian Feng, Subrata Banik, Derek Huang, Reka Norman, Eric Lai, Shou-Chieh Hsu,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
......................................................................
mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
This patch configures external V1p05/Vnn/VnnSx rails for Uldren
to achieve better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:272829190
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/uldren/overridetree.cb
1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74335/5
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