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Change subject: mb/google/dedede/var/kracko: Add G2touch touchscreen support for Kracko
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Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74307/comment/5b42af9f_2ab5c1a1
PS3, Line 13: BRANCH=firmware-dedede-13606.B
btw, branch should above TEST.
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Change subject: soc/intel/: Implement an API to get ISH version
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/74209/comment/132e8f73_2d51823f
PS5, Line 547: if the latest ISH version is not updated in the CBMEM table
Ah, you meant “not up to date”.
Maybe:
> … if the ISH version in CBMEM table outdated
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Change subject: mb/google/dedede/var/kracko: Add G2touch touchscreen support for Kracko
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Patch Set 3:
(1 comment)
Patchset:
PS3:
Do you want add SSFC for FW config?
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Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
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Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74335/comment/753b4e3f_2254f725
PS4, Line 16:
From above:
> … to achieve better power savings
It’d be great if you could clarify then. Maybe:
> … to follow best practices for power savings – untested though.
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Change subject: mb/google/dedede/var/kracko: Add G2touch touchscreen support for Kracko
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74307/comment/750d9582_88b74d11
PS3, Line 11: BUG=b:
trackerID?
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Change subject: mb/google/dedede/var/kracko: Add G2touch touchscreen support for Kracko
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Set Ready For Review
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Change subject: Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"
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Patch Set 4:
(1 comment)
Patchset:
PS4:
> Your revert would be going back to: […]
Well, the "end result" should be not having both Kconfig and devicetree for the same thing for both D3 and s0ix, as already mentioned on CB:72800, CB:73903. This should have been properly designed in the first place tbh, either by only using Kconfig (dropping dt) or by making use of the acpi gen.
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Change subject: soc/intel/mtl: Add meteorlake B0 stepping CPU ID
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Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74300/comment/f3f45213_23c9cd75
PS1, Line 7: soc/intel/mtl:
soc/intel/meteorlake:
https://review.coreboot.org/c/coreboot/+/74300/comment/a324db31_7b32c20f
PS1, Line 7: meteorlake
drop this
https://review.coreboot.org/c/coreboot/+/74300/comment/6adab657_d386138a
PS1, Line 8:
> If you have the source handy, please document it in the commit message.
please mention the doc number and a test line
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Change subject: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
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Patch Set 6:
(1 comment)
File src/mainboard/google/rex/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/74229/comment/c9fb835e_c1830d94
PS1, Line 7: 7M
> I am sorry, I miscalculated 7 * 1024 and thought it’s 7092K instead of 7168K. […]
no problem, appreciate ur time here
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Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table
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Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/74221/comment/1f21af72_a2d2152d
PS1, Line 273: acpi_create_dmar_ds_pci
> You are not checking if the device is enabled or not. […]
valid point.
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