coreboot-gerrit April 2023

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[M] Change in coreboot[master]: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
by build bot (Jenkins) (Code Review) 14 Apr '23

14 Apr '23

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[M] Change in coreboot[master]: cpu,soc/intel: Separate single SSDT CPU entry
by build bot (Jenkins) (Code Review) 14 Apr '23

14 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74399 ) Change subject: cpu,soc/intel: Separate single SSDT CPU entry ...................................................................... Patch Set 2: Verified+1 (1 comment) File src/cpu/intel/haswell/acpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174177): https://review.coreboot.org/c/coreboot/+/74399/comment/b470f861_a714fe07 PS2, Line 328: static void generate_cpu_entry(const struct device *device, int cpu, int core, int cores_per_package) line length of 101 exceeds 100 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/74399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Gerrit-Change-Number: 74399 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 14 Apr 2023 08:54:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Jonathan Zhang, Matt DeVillier, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Fred Reitberger, Felix Held, Tim Chu. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74430 ) Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields ...................................................................... ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields After the obsoletion of Processor() it is necessary to provide _CST package to define P_BLK IO address for C2/C3 transitions. Therefore, the latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 13 files changed, 19 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/74430/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index de5abe0..88e503e 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1682,6 +1682,10 @@ /* should be 0 ACPI 3.0 */ fadt->reserved = 0; + /* P_LVLx not used as CPU _CST will override them. */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); if (CONFIG(USE_PC_CMOS_ALTCENTURY)) diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index b8ac827..7b8393b 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -72,10 +72,6 @@ fill_fadt_extended_pm_regs(fadt); - /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 49fb658..5eae366 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -75,10 +75,6 @@ fill_fadt_extended_pm_regs(fadt); - /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 83b24ec..6228777 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -74,10 +74,6 @@ fill_fadt_extended_pm_regs(fadt); - /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 8e90d44..514ed0e 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -75,10 +75,6 @@ fill_fadt_extended_pm_regs(fadt); - /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a6f1ebd..1a995be 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -80,10 +80,6 @@ fill_fadt_extended_pm_regs(fadt); - /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index caa6496..dfa7d61 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -74,10 +74,6 @@ fill_fadt_extended_pm_regs(fadt); - /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the PSTATE SSDT. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = RTC_DATE_ALARM; diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index c609f4f..0233c37 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -48,8 +48,6 @@ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm2_cnt_len = 1; fadt->gpe0_blk = pmbase + 0x60; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 4989d6b..fe286fe 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -44,8 +44,6 @@ fadt->pm_tmr_len = 4; /* 32 bits */ fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index be315af..a9e7a36 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -31,9 +31,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - /* P_LVLx not used */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index fc3258a..681d09c 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -36,8 +36,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index 9921b4d..d6084ee 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -31,9 +31,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - /* P_LVLx not used */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index fc08f01..ba9439c 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -44,9 +44,6 @@ else fadt->gpe0_blk_len = 2 * 8; - /* P_LVLx not used */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 0; fadt->duty_width = 0; fadt->day_alrm = 0xd; -- To view, visit https://review.coreboot.org/c/coreboot/+/74430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Gerrit-Change-Number: 74430 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74409 ) Change subject: sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines ...................................................................... sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 4 files changed, 18 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74409/1 diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index f625198..be315af 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -32,8 +32,8 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; /* P_LVLx not used */ - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 1d640f4..fc3258a 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -36,8 +36,8 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ - fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index 13243af..9921b4d 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -32,8 +32,8 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; /* P_LVLx not used */ - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index 2051223..fc08f01 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -45,8 +45,8 @@ fadt->gpe0_blk_len = 2 * 8; /* P_LVLx not used */ - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 0; fadt->duty_width = 0; fadt->day_alrm = 0xd; -- To view, visit https://review.coreboot.org/c/coreboot/+/74409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15 Gerrit-Change-Number: 74409 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/intel/speedstep: Separate single SSDT CPU entry
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74400 to look at the new patch set (#3). Change subject: cpu/intel/speedstep: Separate single SSDT CPU entry ...................................................................... cpu/intel/speedstep: Separate single SSDT CPU entry Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/speedstep/acpi.c M src/southbridge/intel/i82371eb/acpi_tables.c 2 files changed, 68 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/74400/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Gerrit-Change-Number: 74400 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: src/arch/x86 Add CPU frequency APIs
by Paul Menzel (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Wonkyu Kim. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74389 ) Change subject: src/arch/x86 Add CPU frequency APIs ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74389/comment/44002a47_7ed41f6a PS1, Line 7: src/arch/x86 Please add a colon after the prefix. https://review.coreboot.org/c/coreboot/+/74389/comment/671e50d2_2182b01f PS1, Line 7: src/ Remove. https://review.coreboot.org/c/coreboot/+/74389/comment/e55c258d_c424e32b PS1, Line 8: Please elaborate, what that API is needed for. -- To view, visit https://review.coreboot.org/c/coreboot/+/74389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eb4397b4a8d4058af1b5c67716ee625261c4e2a Gerrit-Change-Number: 74389 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 08:48:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Adjust I2Cs CLK to be around 400 kHz
by Eric Lai (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jamie Chen, Tarun Tuli, Subrata Banik, Kyle Lin, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74393 ) Change subject: mb/google/brya/var/omnigul: Adjust I2Cs CLK to be around 400 kHz ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74393/comment/13521f04_2dbafae0 PS2, Line 13: 293 > EE reply : the measure value is on the spec. I would suggest near 380 is better. But your call. -- To view, visit https://review.coreboot.org/c/coreboot/+/74393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c4fdf0e003318a69b870b487a60accefbc0ffed Gerrit-Change-Number: 74393 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 08:47:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/cbfstool: Qualify struct e820entry as packed
by Paul Menzel (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Bill XIE. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74270 ) Change subject: util/cbfstool: Qualify struct e820entry as packed ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09955c90e4eec337adca383e628a8821075381d6 Gerrit-Change-Number: 74270 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Fri, 14 Apr 2023 08:46:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel/speedstep: Refactor P-state coordination
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74398 ) Change subject: cpu/intel/speedstep: Refactor P-state coordination ...................................................................... cpu/intel/speedstep: Refactor P-state coordination Change-Id: I12462f271821d3d8fe3324d84a65c2341729591e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/speedstep/acpi.c 1 file changed, 26 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index acca77e..0d2cc87 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -60,6 +60,16 @@ acpigen_write_PPC(0); } +static uint8_t get_p_state_coordination(void) +{ + /* For Penryn use HW_ALL. */ + if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067) + return HW_ALL; + + /* Use SW_ANY as that was the default. */ + return SW_ANY; +} + /** * @brief Generate ACPI entries for Speedstep for each cpu */ @@ -71,22 +81,17 @@ int numcpus = totalcores/cores_per_package; /* This assumes that all CPUs share the same layout. */ + int num_cstates; const acpi_cstate_t *cstates; sst_table_t pstates; - uint8_t coordination; + uint8_t coordination = get_p_state_coordination(); printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); num_cstates = get_cst_entries(&cstates); speedstep_gen_pstates(&pstates); - if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067) - /* For Penryn use HW_ALL. */ - coordination = HW_ALL; - else - /* Use SW_ANY as that was the default. */ - coordination = SW_ANY; for (cpuID = 0; cpuID < numcpus; ++cpuID) { for (coreID = 1; coreID <= cores_per_package; coreID++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12462f271821d3d8fe3324d84a65c2341729591e Gerrit-Change-Number: 74398 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/intel/speedstep: Refactor P-state coordination
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74398 ) Change subject: cpu/intel/speedstep: Refactor P-state coordination ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12462f271821d3d8fe3324d84a65c2341729591e Gerrit-Change-Number: 74398 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 08:38:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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