Attention is currently required from: Tarun Tuli, SRIDHAR SIRICILLA, Subrata Banik, Kapil Porwal, Dinesh Gehlot.
Hello build bot (Jenkins), Tarun Tuli, SRIDHAR SIRICILLA, Kangheui Won, Kapil Porwal, Dinesh Gehlot,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static
......................................................................
soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static
The patch makes `cse_get_fpt_partition_info()` AP local/static as all
the references to this function are in local to the cse_lite.c file.
BUG=b:273661726
TEST=Able to build and boot google/marasov with this code change.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac
---
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 18 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74388/3
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Subrata Banik has uploaded a new patch set (#15) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74209 )
Change subject: drivers/intel/ish: Hook get ISH version into `.final`
......................................................................
drivers/intel/ish: Hook get ISH version into `.final`
This patch creates .final hook to call into get ISH version function
if platform has required config
(`SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION`) support.
BUG=b:273661726
TEST=The ISHC version, 5.4.2.7779, was retrieved on the google/nivviks.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8
---
M src/drivers/intel/ish/ish.c
1 file changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74209/15
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74403 )
Change subject: soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT
......................................................................
Set Ready For Review
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74343 )
Change subject: security/vboot: Add function to clear recovery request
......................................................................
Patch Set 3:
(1 comment)
File src/security/vboot/bootmode.c:
https://review.coreboot.org/c/coreboot/+/74343/comment/3682bc7d_e600444e
PS3, Line 31: save_vbnv
Do we need to save nvdata here in this function? Usually it should be sufficient to save nvdata right before rebooting (for example `vboot_save_and_reboot`), or before handoff to the next boot stage (for ChromeOS we do this in depthcharge before handoff to kernel), instead of having to save it for each nvdata change.
I wonder if we can extend `BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, back_up_vbnv_cmos)` to also saving nvdata, when some Kconfig option `VBOOT_SAVE_VBNV_BEFORE_PAYLOAD` is enabled (and only when `VB2_CONTEXT_NVDATA_CHANGED`).
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74382 )
Change subject: soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.c
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74382/comment/7a40ad86_d6a27a88
PS1, Line 9: The patch moves API that gets the CSE FW partition information into
: CSE Lite specific file aka cse_lite.c because the consumer of this API
: is the cse_lite specific ChromeOS devices hence, it's meaningful to
: move the cse lite specific implementation inside cse_lite.c file.
cse.c represents library, provides API. I don't see any need to move the GET IMAGE FW INFO command handler into cse_lite.c. I request you to reconsider the option of moving the API into cse_lite.c. Thanks!
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74416
to look at the new patch set (#4).
Change subject: mb/google/dedede/var/boten: Generate SPD ID for supported memory part
......................................................................
mb/google/dedede/var/boten: Generate SPD ID for supported memory part
Add boten supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K4U6E3S4AB-MGCL
BUG=b:278138388
TEST=Use part_id_gen to generate related settings
Signed-off-by: kevin3.yang <kevin3.yang(a)lcfc.corp-partner.google.com>
Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6
---
M src/mainboard/google/dedede/variants/boten/memory/Makefile.inc
M src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt
3 files changed, 23 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/74416/4
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Change subject: mb/google/dedede/var/boten: Generate SPD ID for supported memory part
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74398 )
Change subject: cpu/intel/speedstep: Refactor P-state coordination
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/intel/speedstep/acpi.c:
https://review.coreboot.org/c/coreboot/+/74398/comment/5a7002cc_0a777f57
PS1, Line 66: ((cpuid_eax(1) >> 4) & 0xffff) == 0x1067
> This code should be checked for validity. Is it really about the model or hyperthreading?
No hyperthreading on that model. I have no idea...
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Simon Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74391 )
Change subject: mb/google/rex: Create screebo variant
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Patchset 4 is regenerated by `create_variant.sh rex rex0 screebo b:276814951` after cherry-picking https://review.coreboot.org/c/coreboot/+/74257. Please help review again, thank you~
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