coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Maximilian Brune. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73736 ) Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73736/comment/4cb736ed_a523e782 PS1, Line 9: to optimize the boot time > Please add hard numbers and the platform you tested with. Sorry I dont have any data by hand, however did test on several boards and it works, will add that. https://review.coreboot.org/c/coreboot/+/73736/comment/5f8ec910_c85c68a3 PS1, Line 12: For further details, please refer to: > Please summarize the details. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 11:08:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Maximilian Brune, Lean Sheng Tan. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Maximilian Brune, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73736 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... soc/intel/alderlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/73736/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Maximilian Brune, Lean Sheng Tan. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Maximilian Brune, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73736 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... soc/intel/alderlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_TOM` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/73736/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of TOM region
by build bot (Jenkins) (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Maximilian Brune, Lean Sheng Tan. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73736 ) Change subject: soc/intel/alderlake: Enable early caching of TOM region ...................................................................... Patch Set 4: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174185): https://review.coreboot.org/c/coreboot/+/73736/comment/ae501394_8af55c08 PS4, Line 12: For further details, please refer to: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit bc8bbeed3b8a ("soc/intel/cmn/tom: Cache TOM region early")' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174185): https://review.coreboot.org/c/coreboot/+/73736/comment/a64d58bb_52d43079 PS4, Line 13: commit bc8bbee Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 725dd39f5b91 ("soc/intel/cmn/sa: Store TOM into the CMOS")' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174185): https://review.coreboot.org/c/coreboot/+/73736/comment/08c8ee1c_7d986bd8 PS4, Line 14: commit 725dd39 Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit dbfbfaf608c3 ("drivers/intel/fsp2_0: Have provision for caching TOM region")' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174185): https://review.coreboot.org/c/coreboot/+/73736/comment/c4476766_4c92d54c PS4, Line 15: commit dbfbfaf Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 01209524f4b3 ("soc/intel/meteorlake: Enable early caching of TOM region")' -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 11:06:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of TOM region
by build bot (Jenkins) (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Maximilian Brune, Lean Sheng Tan. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73736 ) Change subject: soc/intel/alderlake: Enable early caching of TOM region ...................................................................... Patch Set 3: Verified+1 (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/a5e4bf02_22199db8 PS3, Line 12: For further details, please refer to: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit bc8bbeed3b8a ("soc/intel/cmn/tom: Cache TOM region early")' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/da9ee74f_6843e8f6 PS3, Line 13: commit bc8bbee Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 725dd39f5b91 ("soc/intel/cmn/sa: Store TOM into the CMOS")' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/ffe8b3a1_0ad0700c PS3, Line 14: commit 725dd39 Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit dbfbfaf608c3 ("drivers/intel/fsp2_0: Have provision for caching TOM region")' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/e2dd6675_adacf26b PS3, Line 15: commit dbfbfaf Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 01209524f4b3 ("soc/intel/meteorlake: Enable early caching of TOM region")' -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 11:05:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming). Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/xeon_sp/memmap.c: https://review.coreboot.org/c/coreboot/+/71085/comment/efffd0e1_0d446448 PS2, Line 41: /* Cache the TSEG region */ : if (CONFIG(TSEG_STAGE_CACHE)) : postcar_enable_tseg_cache(pcf); This is included in the previous one. -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 11:02:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming). Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 10:53:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming). Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71085/comment/66ab3ae0_7e151125 PS2, Line 7: boottime boot time -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 10:51:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) ( 29 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... soc/intel/xeon_sp: Don't sort struct device cpus for numa Currently the xeon_sp code reassigns struct devices apic_id so that srat entries can be added in a certain order. This is not a good idea as it breaks thread local storage which contains a pointer to its struct device cpu. This moves the sorting of the lapic_ids to the srat table generation and adds the numa node id in each core init entry. Now it is done in parallel too as a bonus. Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/soc/intel/xeon_sp/util.c 5 files changed, 62 insertions(+), 120 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index f46d1a6..14535e2 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -78,8 +78,9 @@ { msr_t msr; - printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, + cpu->path.apic.package_id); /* * Set HWP base feature, EPP reg enumeration, lock thermal and msr @@ -227,7 +228,4 @@ * rest of the CPU devices do not have chip_info updated. */ chip_config = bus->dev->chip_info; - - /* update numa domain for all cpu devices */ - xeonsp_init_cpu_config(); } diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 52afc48..a828ffc 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -13,7 +13,6 @@ int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); -void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); uint8_t soc_get_iio_ioapicid(int socket, int stack); diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index a9a035d..009527c 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -59,8 +59,9 @@ { msr_t msr; - printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, + cpu->path.apic.package_id); assert(chip_config); /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ @@ -247,8 +248,5 @@ /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(bus, &mp_ops); - /* update numa domain for all cpu devices */ - xeonsp_init_cpu_config(); - FUNC_EXIT(); } diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index be46504..e2b262e 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -6,6 +6,7 @@ #include <assert.h> #include <cbmem.h> #include <cpu/x86/lapic.h> +#include <commonlib/sort.h> #include <device/mmio.h> #include <device/pci.h> #include <device/pciexp.h> @@ -22,29 +23,54 @@ /* NUMA related ACPI table generation. SRAT, SLIT, etc */ +/* Increase if necessary. Currently all x86 CPUs only have 2 SMP threads */ +#define MAX_THREAD 2 + unsigned long acpi_create_srat_lapics(unsigned long current) { struct device *cpu; - unsigned int cpu_index = 0; + unsigned int num_cpus = 0; + int apic_ids[CONFIG_MAX_CPUS] = {}; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (!is_enabled_cpu(cpu)) + unsigned int sort_start = 0; + for (unsigned int thread_id = 0; thread_id < MAX_THREAD; thread_id++) { + for (cpu = all_devices; cpu; cpu = cpu->next) { + if (!is_enabled_cpu(cpu)) + continue; + if (num_cpus >= ARRAY_SIZE(apic_ids)) + break; + if (cpu->path.apic.thread_id != thread_id) + continue; + apic_ids[num_cpus++] = cpu->path.apic.apic_id; + } + bubblesort(&apic_ids[sort_start], num_cpus - sort_start, NUM_ASCENDING); + sort_start = num_cpus; + } + + for (unsigned int i = 0; i < num_cpus; i++) { + /* Match the sorted apic_ids to a struct device */ + for (cpu = all_devices; cpu; cpu = cpu->next) { + if (!is_enabled_cpu(cpu)) + continue; + if (cpu->path.apic.apic_id == apic_ids[i]) + break; + } + if (!cpu) continue; if (is_x2apic_mode()) { - printk(BIOS_DEBUG, "SRAT: x2apic cpu_index=%08x, node_id=%02x, apic_id=%08x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + printk(BIOS_DEBUG, "SRAT: x2apic cpu_index=%04x, node_id=%02x, apic_id=%08x\n", + i, cpu->path.apic.node_id, cpu->path.apic.apic_id); current += acpi_create_srat_x2apic((acpi_srat_x2apic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id); } else { printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + i, cpu->path.apic.node_id, cpu->path.apic.apic_id); current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id); } - cpu_index++; } return current; } diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 7524e52..e0bf9bc 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -125,108 +125,6 @@ } #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ -static void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - register int ecx; - struct cpuid_result cpuid_regs; - - /* get max index of CPUID */ - cpuid_regs = cpuid(0); - assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ - - *thread_bits = *core_bits = 0; - ecx = 0; - while (1) { - cpuid_regs = cpuid_ext(0xb, ecx); - if (ecx == 0) { - *thread_bits = (cpuid_regs.eax & 0x1f); - } else { - *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; - break; - } - ecx++; - } -} - -static void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread) -{ - if (package) - *package = (apicid >> (thread_bits + core_bits)); - if (core) - *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); - if (thread) - *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); -} - -void xeonsp_init_cpu_config(void) -{ - struct device *dev; - int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; - int num_apics = 0; - uint32_t core_bits, thread_bits; - unsigned int core_count, thread_count; - unsigned int num_sockets; - - /* - * sort APIC ids in ascending order to identify apicid ranges for - * each numa domain - */ - for (dev = all_devices; dev; dev = dev->next) { - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - apic_ids[num_apics++] = dev->path.apic.apic_id; - } - if (num_apics > 1) - bubblesort(apic_ids, num_apics, NUM_ASCENDING); - - num_sockets = soc_get_num_cpus(); - cpu_read_topology(&core_count, &thread_count); - assert(num_apics == (num_sockets * thread_count)); - - /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ - int index = 0; - for (int id = 0; id < num_apics; ++id) { - int apic_id = apic_ids[id]; - if (apic_id & 0x1) { /* 2nd thread */ - apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; - } else { /* 1st thread */ - apic_ids_by_thread[index++] = apic_id; - } - } - - /* update apic_id, node_id in sorted order */ - num_apics = 0; - get_core_thread_bits(&core_bits, &thread_bits); - for (dev = all_devices; dev; dev = dev->next) { - uint8_t package; - - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; - get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, - &package, NULL, NULL); - dev->path.apic.node_id = package; - printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", - num_apics, dev->path.apic.apic_id, - dev->path.apic.apic_id, dev->path.apic.node_id); - - ++num_apics; - } -} - /* return true if command timed out else false */ static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, uint32_t target) -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 33 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/rex: Create screebo variant
by Kapil Porwal (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Simon Zhou. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74391 ) Change subject: mb/google/rex: Create screebo variant ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Gerrit-Change-Number: 74391 Gerrit-PatchSet: 4 Gerrit-Owner: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 10:41:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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