coreboot-gerrit April 2023

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[M] Change in coreboot[master]: Revert "soc/intel/xeon_sp: Don't sort struct device cpus for numa"
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jonathan Zhang, Simon Chou, Paul Menzel, Angel Pons, Arthur Heymans, TangYiwei, Patrick Rudolph, Lance Zhao, Anjaneya "Reddy" Chagam, Johnny Lin, Ziang Wang, Tim Wawrzynczak, Christian Walter. Hello build bot (Jenkins), Simon Chou, Jonathan Zhang, Paul Menzel, Angel Pons, Arthur Heymans, TangYiwei, Patrick Rudolph, Lance Zhao, Anjaneya "Reddy" Chagam, Johnny Lin, Ziang Wang, Tim Wawrzynczak, Christian Walter, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/73908 to review the following change. Change subject: Revert "soc/intel/xeon_sp: Don't sort struct device cpus for numa" ...................................................................... Revert "soc/intel/xeon_sp: Don't sort struct device cpus for numa" This reverts commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. The jenkins is broken due to this. Change-Id: I371d9c3ab9351c1e60685e2210c9dbaaac23f09d Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/soc/intel/xeon_sp/util.c 5 files changed, 134 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/73908/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 14535e2..f46d1a6 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -78,9 +78,8 @@ { msr_t msr; - printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, - cpu->path.apic.package_id); + printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); /* * Set HWP base feature, EPP reg enumeration, lock thermal and msr @@ -228,4 +227,7 @@ * rest of the CPU devices do not have chip_info updated. */ chip_config = bus->dev->chip_info; + + /* update numa domain for all cpu devices */ + xeonsp_init_cpu_config(); } diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index a828ffc..52afc48 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -13,6 +13,7 @@ int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); +void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); uint8_t soc_get_iio_ioapicid(int socket, int stack); diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 009527c..a9a035d 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -59,9 +59,8 @@ { msr_t msr; - printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, - cpu->path.apic.package_id); + printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); assert(chip_config); /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ @@ -248,5 +247,8 @@ /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(bus, &mp_ops); + /* update numa domain for all cpu devices */ + xeonsp_init_cpu_config(); + FUNC_EXIT(); } diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index e2b262e..be46504 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -6,7 +6,6 @@ #include <assert.h> #include <cbmem.h> #include <cpu/x86/lapic.h> -#include <commonlib/sort.h> #include <device/mmio.h> #include <device/pci.h> #include <device/pciexp.h> @@ -23,54 +22,29 @@ /* NUMA related ACPI table generation. SRAT, SLIT, etc */ -/* Increase if necessary. Currently all x86 CPUs only have 2 SMP threads */ -#define MAX_THREAD 2 - unsigned long acpi_create_srat_lapics(unsigned long current) { struct device *cpu; - unsigned int num_cpus = 0; - int apic_ids[CONFIG_MAX_CPUS] = {}; + unsigned int cpu_index = 0; - unsigned int sort_start = 0; - for (unsigned int thread_id = 0; thread_id < MAX_THREAD; thread_id++) { - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (!is_enabled_cpu(cpu)) - continue; - if (num_cpus >= ARRAY_SIZE(apic_ids)) - break; - if (cpu->path.apic.thread_id != thread_id) - continue; - apic_ids[num_cpus++] = cpu->path.apic.apic_id; - } - bubblesort(&apic_ids[sort_start], num_cpus - sort_start, NUM_ASCENDING); - sort_start = num_cpus; - } - - for (unsigned int i = 0; i < num_cpus; i++) { - /* Match the sorted apic_ids to a struct device */ - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (!is_enabled_cpu(cpu)) - continue; - if (cpu->path.apic.apic_id == apic_ids[i]) - break; - } - if (!cpu) + for (cpu = all_devices; cpu; cpu = cpu->next) { + if (!is_enabled_cpu(cpu)) continue; if (is_x2apic_mode()) { - printk(BIOS_DEBUG, "SRAT: x2apic cpu_index=%04x, node_id=%02x, apic_id=%08x\n", - i, cpu->path.apic.node_id, cpu->path.apic.apic_id); + printk(BIOS_DEBUG, "SRAT: x2apic cpu_index=%08x, node_id=%02x, apic_id=%08x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); current += acpi_create_srat_x2apic((acpi_srat_x2apic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id); } else { printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - i, cpu->path.apic.node_id, cpu->path.apic.apic_id); + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id); } + cpu_index++; } return current; } diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index e0bf9bc..7524e52 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -125,6 +125,108 @@ } #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ +static void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) +{ + register int ecx; + struct cpuid_result cpuid_regs; + + /* get max index of CPUID */ + cpuid_regs = cpuid(0); + assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ + + *thread_bits = *core_bits = 0; + ecx = 0; + while (1) { + cpuid_regs = cpuid_ext(0xb, ecx); + if (ecx == 0) { + *thread_bits = (cpuid_regs.eax & 0x1f); + } else { + *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; + break; + } + ecx++; + } +} + +static void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, + uint8_t *package, uint8_t *core, uint8_t *thread) +{ + if (package) + *package = (apicid >> (thread_bits + core_bits)); + if (core) + *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); + if (thread) + *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); +} + +void xeonsp_init_cpu_config(void) +{ + struct device *dev; + int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; + int num_apics = 0; + uint32_t core_bits, thread_bits; + unsigned int core_count, thread_count; + unsigned int num_sockets; + + /* + * sort APIC ids in ascending order to identify apicid ranges for + * each numa domain + */ + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + apic_ids[num_apics++] = dev->path.apic.apic_id; + } + if (num_apics > 1) + bubblesort(apic_ids, num_apics, NUM_ASCENDING); + + num_sockets = soc_get_num_cpus(); + cpu_read_topology(&core_count, &thread_count); + assert(num_apics == (num_sockets * thread_count)); + + /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ + int index = 0; + for (int id = 0; id < num_apics; ++id) { + int apic_id = apic_ids[id]; + if (apic_id & 0x1) { /* 2nd thread */ + apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; + } else { /* 1st thread */ + apic_ids_by_thread[index++] = apic_id; + } + } + + /* update apic_id, node_id in sorted order */ + num_apics = 0; + get_core_thread_bits(&core_bits, &thread_bits); + for (dev = all_devices; dev; dev = dev->next) { + uint8_t package; + + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; + get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, + &package, NULL, NULL); + dev->path.apic.node_id = package; + printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", + num_apics, dev->path.apic.apic_id, + dev->path.apic.apic_id, dev->path.apic.node_id); + + ++num_apics; + } +} + /* return true if command timed out else false */ static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, uint32_t target) -- To view, visit https://review.coreboot.org/c/coreboot/+/73908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I371d9c3ab9351c1e60685e2210c9dbaaac23f09d Gerrit-Change-Number: 73908 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
by Nico Huber (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Sridhar Siricilla, Arthur Heymans, Kyösti Mälkki, Fred Reitberger, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74316 ) Change subject: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC ...................................................................... Patch Set 3: Code-Review+1 (3 comments) Patchset: PS3: +2 File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74316/comment/b8bd46a5_e5661afd PS2, Line 296: if (CONFIG(ACPI_COMMON_MADT_LAPIC)) > Further work on asus/p2b could land in CB:74348 ? I guess so. IIRC, the boards are maintained by Keith and Branden, please add them, at least if changes should be tested. File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74316/comment/28e30d8c_ff330229 PS2, Line 90: ACPI_COMMON_MADT_LAPIC > ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID) += cpu_hybrid.c […] Ack. -- To view, visit https://review.coreboot.org/c/coreboot/+/74316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Gerrit-Change-Number: 74316 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Apr 2023 11:50:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled
by Sean Rhodes (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 ) Change subject: soc/intel/common: Fix long delay when ME is disabled ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/74435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Gerrit-Change-Number: 74435 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 11:28:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Disable C-States & cTDP
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Lean Sheng Tan has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/68222 ) Change subject: mb/prodrive/atlas: Disable C-States & cTDP ...................................................................... Abandoned not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/68222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1c15ac258c78025420966bf592795b66101d17 Gerrit-Change-Number: 68222 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: mb/lenovo/x200: Configure ck505 clockgen
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Arthur Heymans, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Bill XIE, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74418 to look at the new patch set (#5). Change subject: mb/lenovo/x200: Configure ck505 clockgen ...................................................................... mb/lenovo/x200: Configure ck505 clockgen The clockgen is behind an smbus mux which is implemented with a gpio. This adds a callback inside the ck505 code to configure the mux. The clockgen configuration values are taken from dumping the clockgen with vendor firmware. TESTED on x200 and x301: boots fine Change-Id: Iec9bbbaed43b74e8782f6963e491dbfa3b8b5247 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/drivers/i2c/ck505/ck505.c A src/drivers/i2c/ck505/ck505.h M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x200/variants/x200/overridetree.cb M src/mainboard/lenovo/x200/variants/x301/overridetree.cb 6 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/74418/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9bbbaed43b74e8782f6963e491dbfa3b8b5247 Gerrit-Change-Number: 74418 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/tigerlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Lean Sheng Tan. Hello build bot (Jenkins), Sean Rhodes, Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73738 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Enable early caching of RAMTOP region ...................................................................... soc/intel/tigerlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/73738/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Gerrit-Change-Number: 73738 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/lenovo/x200: Configure ck505 clockgen
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Stefan Ott, Arthur Heymans, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74418 to look at the new patch set (#4). Change subject: mb/lenovo/x200: Configure ck505 clockgen ...................................................................... mb/lenovo/x200: Configure ck505 clockgen The clockgen is behind an smbus mux which is implemented with a gpio. This adds a callback inside the ck505 code to configure the mux. The clockgen configuration values are taken from dumping the clockgen with vendor firmware. TESTED on x200 and x301: boots fine Change-Id: Iec9bbbaed43b74e8782f6963e491dbfa3b8b5247 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/i2c/ck505/ck505.c A src/drivers/i2c/ck505/ck505.h M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x200/variants/x200/overridetree.cb M src/mainboard/lenovo/x200/variants/x301/overridetree.cb 6 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/74418/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9bbbaed43b74e8782f6963e491dbfa3b8b5247 Gerrit-Change-Number: 74418 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Maximilian Brune. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Maximilian Brune, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73736 to look at the new patch set (#8). Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... soc/intel/alderlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot Starlab ADL laptop to OS. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/73736/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 8 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Maximilian Brune. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Maximilian Brune, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73736 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... soc/intel/alderlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot Starlab ADL laptop to OS. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/73736/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Mainboard/lenovo/x200: Configure ck505 clockgen
by Bill XIE (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Stefan Ott, Arthur Heymans, Alexander Couzens. Bill XIE has uploaded a new patch set (#3) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/74418 ) Change subject: Mainboard/lenovo/x200: Configure ck505 clockgen ...................................................................... Mainboard/lenovo/x200: Configure ck505 clockgen The clockgen is behind an smbus mux which is implemented with a gpio. This adds a callback inside the ck505 code to configure the mux. TESTED on x200: boots fine TESTED on x301: boots fine Change-Id: Iec9bbbaed43b74e8782f6963e491dbfa3b8b5247 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/i2c/ck505/ck505.c A src/drivers/i2c/ck505/ck505.h M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x200/variants/x200/overridetree.cb M src/mainboard/lenovo/x200/variants/x301/overridetree.cb 6 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/74418/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9bbbaed43b74e8782f6963e491dbfa3b8b5247 Gerrit-Change-Number: 74418 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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