coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled
by Paul Menzel (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik, Sridhar Siricilla, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 ) Change subject: soc/intel/common: Fix long delay when ME is disabled ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74435/comment/4c9b8be7_21920339 PS1, Line 14: : This is because the current code only checks if the ME is : disabled for CSE LITE SKUs. With this patch, boot times are : approximately 5 seconds quicker: > sorry I didn't understand how existing code is delaying the boot time, can you please share more inf […] So `cse_is_hfs1_com_soft_temp_disable()` took that long, and is skipped now with your patch from `&&` to `||`? -- To view, visit https://review.coreboot.org/c/coreboot/+/74435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Gerrit-Change-Number: 74435 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:50:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
by Paul Menzel (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Arthur Heymans, Shuming Chu (Shuming). Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform ...................................................................... Patch Set 4: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71085/comment/70799696_e5e29d5f PS4, Line 7: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform Maybe: > soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S boot time https://review.coreboot.org/c/coreboot/+/71085/comment/5684fc6d_a11f7863 PS4, Line 12: Maybe paste the MTRR before and after for easy comparison? https://review.coreboot.org/c/coreboot/+/71085/comment/eb9799c5_ca2b60f6 PS4, Line 13: TESTED on Archer City 2S: Boottime goes from ~19m to ~4m. Minutes or seconds? ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 4 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:47:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for...
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Lean Sheng Tan, Naresh Solanki, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74436 ) Change subject: soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for numa ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:46:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming). Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/xeon_sp/memmap.c: https://review.coreboot.org/c/coreboot/+/71085/comment/1c4915a9_b15099fe PS2, Line 34: * So set up MTRR to cover the full memory < 4G with WB. > > from what I understand it only covers 0-TSEG, not the full memory < 4G. […] Done https://review.coreboot.org/c/coreboot/+/71085/comment/b62ada2f_31130be2 PS2, Line 41: /* Cache the TSEG region */ : if (CONFIG(TSEG_STAGE_CACHE)) : postcar_enable_tseg_cache(pcf); > This is included in the previous one. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:43:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming). Arthur Heymans has uploaded a new patch set (#4) to the change originally created by Shuming Chu (Shuming). ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform ...................................................................... soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform Set up a postcar MTRR solution that caches the full DRAM including TSEG. FSP-S uses memory above cbmem_top and below TSEG base. Caching that region dramatically improves boottimes. TESTED on Archer City 2S: Boottime goes from ~19m to ~4m. Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M src/soc/intel/xeon_sp/memmap.c 1 file changed, 24 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/71085/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 4 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming). Arthur Heymans has uploaded a new patch set (#3) to the change originally created by Shuming Chu (Shuming). ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform ...................................................................... soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform Set up a postcar MTRR solution that caches the full DRAM including TSEG. FSP-S uses memory above cbmem_top and below TSEG base. Caching that region dramatically improves boottimes. TESTED on Archer City 2S: Boottime goes from ~19m to ~4m. Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M src/soc/intel/xeon_sp/memmap.c 1 file changed, 24 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/71085/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled
by Sridhar Siricilla (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik, Angel Pons. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 ) Change subject: soc/intel/common: Fix long delay when ME is disabled ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74435/comment/35c62da0_f9b84da6 PS1, Line 14: : This is because the current code only checks if the ME is : disabled for CSE LITE SKUs. With this patch, boot times are : approximately 5 seconds quicker: sorry I didn't understand how existing code is delaying the boot time, can you please share more info? -- To view, visit https://review.coreboot.org/c/coreboot/+/74435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Gerrit-Change-Number: 74435 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:41:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Felix Held (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: Code-Review-1 (1 comment) File src/vendorcode/amd/fsp/phoenix/platform_descriptors.h: https://review.coreboot.org/c/coreboot/+/74378/comment/e4351351_4c8dd46f PS1, Line 194: uint32_t link_speed_capability :2; // See dxio_link_speed_cap > using GEN4 enum value overflows this field oh, this is a 3 bit field in agesa while it's still a 2 bit field in coreboot. i'll rework this -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:38:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu,soc/intel: Sync ACPI CPU object implementations
by Felix Held (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74396 ) Change subject: cpu,soc/intel: Sync ACPI CPU object implementations ...................................................................... Patch Set 2: (1 comment) File src/cpu/intel/haswell/acpi.c: https://review.coreboot.org/c/coreboot/+/74396/comment/627bc1dc_d1641caa PS2, Line 337: for (int cpu_id = 0; cpu_id < numcpus; cpu_id++) { it's more common in coreboot to define the local variables at the beginning of the function and not inside the for loop. since we're at a new enough c standard, this isn't really an issue though. i don't have too strong opinions about this, so if you'd like to keep it the way it is right now, fell free to just ack this comment -- To view, visit https://review.coreboot.org/c/coreboot/+/74396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14e1120e74e1bd92acd782a53104fabfb266c3b5 Gerrit-Change-Number: 74396 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Fred Reitberger (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jason Glenesk, Tim Van Patten, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Apr 2023 12:32:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023