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Hello build bot (Jenkins), Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Naresh Solanki, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
......................................................................
soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB
that was caused by the API changed in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6
---
M src/soc/intel/xeon_sp/spr/cpu.c
1 file changed, 16 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74436/4
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Change subject: soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for numa
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/spr/cpu.c:
https://review.coreboot.org/c/coreboot/+/74436/comment/3f6f5b0a_e882d3bf
PS3, Line 83: cpu->path.apic.package_id);
> Yes, I realized that now. One could also write in the commit message that this […]
It is all in the same commit actually.
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Change subject: soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for numa
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https://review.coreboot.org/c/coreboot/+/74436/comment/318f087c_ede05003
PS3, Line 12:
> Would also be nice to have it tested, so it's clear that the issues […]
I dont have the ArchurCity code setup ready to run test on actual hardware.
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Change subject: soc/intel/tigerlake: Enable early caching of RAMTOP region
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Patch Set 4: Code-Review+2
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Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region
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Patch Set 8: Code-Review+2
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Change subject: soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for numa
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PS3, Line 12:
Would also be nice to have it tested, so it's clear that the issues
introduced by the merge of CB:68912 are settled.
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Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
......................................................................
Patch Set 1:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/74430/comment/cd54ab88_aeb895bd
PS1, Line 1685: /* P_LVLx not used as CPU _CST will override them. */
> code indent should use tabs where possible
Please fix.
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Change subject: sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines
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