coreboot-gerrit April 2023

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[M] Change in coreboot[master]: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Jonathan Zhang, Matt DeVillier, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Fred Reitberger, Tim Chu. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74430 ) Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields ...................................................................... Patch Set 2: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74430/comment/06e28024_bcd0f619 PS1, Line 1685: /* P_LVLx not used as CPU _CST will override them. */ > > code indent should use tabs where possible […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Gerrit-Change-Number: 74430 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:17:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
by Nico Huber (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Lean Sheng Tan, Naresh Solanki, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74436 ) Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74436/comment/781f6a84_a0c01cb4 PS3, Line 12: > I dont have the ArchurCity code setup ready to run test on actual hardware. I don't mind if you go ahead without testing (but only because I'm not affected). This is something you'd get for free with a revert btw.: knowing that you return to a (supposed to be) working state. File src/soc/intel/xeon_sp/spr/cpu.c: https://review.coreboot.org/c/coreboot/+/74436/comment/3027e943_60c2d636 PS3, Line 83: cpu->path.apic.package_id); > It is all in the same commit actually. The commit message should match the changes. Please either update the commit message or the change. -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:15:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd: Clarify ACPI _PRT entry generation
by Felix Held (Code Review) 14 Apr '23

14 Apr '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74314 ) Change subject: soc/amd: Clarify ACPI _PRT entry generation ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/pci/acpi_prt.c: https://review.coreboot.org/c/coreboot/+/74314/comment/a4dc043f_f7dd6fcf PS2, Line 10: /* GNB IO-APIC is located after the FCH IO-APIC */ > Ack i'm ok with revisiting this later. also not sure if Arthur might have some patches for this -- To view, visit https://review.coreboot.org/c/coreboot/+/74314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Gerrit-Change-Number: 74314 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:14:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device()
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74441 ) Change subject: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device() ...................................................................... [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device() TBD: In case of no _CST entries, add valid _PTC ? Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/speedstep/acpi.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c 4 files changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74441/1 diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 0a13445..b27e29d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -72,8 +72,6 @@ static void generate_cpu_entry(int cpu, int core, int cores_per_package) { - int pcontrol_blk = PMB0_BASE, plen = 6; - static struct { int once; uint8_t coordination; @@ -89,13 +87,8 @@ speedstep_gen_pstates(&s.pstates); } - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx. */ - acpigen_write_processor(cpu * cores_per_package + core, pcontrol_blk, plen); + /* Generate Scope(\_SB) { Device(CPUx */ + acpigen_write_processor_device(cpu * cores_per_package + core); /* Generate p-state entries. */ gen_pstate_entries(&s.pstates, cpu, cores_per_package, s.coordination); @@ -104,7 +97,7 @@ if (s.num_cstates > 0) acpigen_write_CST_package(s.cstates, s.num_cstates); - acpigen_pop_len(); + acpigen_write_processor_device_end(); } /** diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 6d63e72..ae9a77f 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -34,6 +34,7 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->duty_offset = 1; @@ -41,6 +42,7 @@ fadt->duty_width = 3; else fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 54ebcbd..5bceffe 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -30,10 +30,12 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 0x39; fadt->duty_offset = 1; fadt->duty_width = 3; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 9d60ca5a..aa60aaf 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -30,10 +30,13 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */ + fadt->duty_offset = 1; fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; -- To view, visit https://review.coreboot.org/c/coreboot/+/74441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Gerrit-Change-Number: 74441 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [WIP] asus/p2b, emulation/qemu-i440fx: Use acpigen_write_processor_de...
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74440 ) Change subject: [WIP] asus/p2b, emulation/qemu-i440fx: Use acpigen_write_processor_device() ...................................................................... [WIP] asus/p2b, emulation/qemu-i440fx: Use acpigen_write_processor_device() FADT P_LVLx had values that disabled C2/C3 state transitions. Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi_tables.c M src/southbridge/intel/i82371eb/fadt.c 2 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74440/1 diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 15f2c429..17ff2ab 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -6,13 +6,13 @@ #include <device/device.h> #include "i82371eb.h" - static void generate_cpu_entry(int cpu) { - int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6; + acpigen_write_processor_device(cpu); - acpigen_write_processor(cpu, pcontrol_blk, plen); - acpigen_pop_len(); + /* TBD: _PTC to communicate clock throttling */ + + acpigen_write_processor_device_end(); } void generate_cpu_entries(const struct device *device) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 681d09c..5122dcf 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -38,6 +38,7 @@ fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ + fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ fadt->mon_alrm = 0x0; /* not supported */ /* -- To view, visit https://review.coreboot.org/c/coreboot/+/74440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Gerrit-Change-Number: 74440 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: aopen/dxplplusu: Drop ACPI C-states support
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74439 ) Change subject: aopen/dxplplusu: Drop ACPI C-states support ...................................................................... aopen/dxplplusu: Drop ACPI C-states support C0 clock throttling was disabled, no need to add _PTC. C2/C3 latency values were copy-paste from different CPUs. TBD: Check IO-trap Change-Id: Ia0e35e28f0df8b0f8fc58f70c7d792487ee4f7f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82801dx/fadt.c 1 file changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/74439/1 diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index fdb7fb3..5b01948 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -25,16 +25,12 @@ fadt->pm1_cnt_len = 2; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 85; - fadt->duty_offset = 1; - fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; -- To view, visit https://review.coreboot.org/c/coreboot/+/74439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e35e28f0df8b0f8fc58f70c7d792487ee4f7f3 Gerrit-Change-Number: 74439 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ACPI: Obsolete FADT duty_offset and duty_width fields
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74438 ) Change subject: ACPI: Obsolete FADT duty_offset and duty_width fields ...................................................................... ACPI: Obsolete FADT duty_offset and duty_width fields After the obsoletion of Processor() it is necessary to provide _PTC package to define P_CNT IO address for clock throttling. The platforms touched here already emit empty _PTC to disable clock throttling. Change-Id: I0e84c8ccd2772c9b3d61f71b74324c8d28f4eefe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 4 files changed, 21 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/74438/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2a258d7..a60e991 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1686,6 +1686,10 @@ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + /* Use CPU _PTC instead to provide P_CNT details. */ + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); if (CONFIG(USE_PC_CMOS_ALTCENTURY)) diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index a9e7a36..296ee2b 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -31,9 +31,7 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - /* P_CNT not supported */ - fadt->duty_offset = 0; - fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index d6084ee..dfb9774 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -31,9 +31,7 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - /* P_CNT not supported */ - fadt->duty_offset = 0; - fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index ba9439c..a90d0a8 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -44,8 +44,6 @@ else fadt->gpe0_blk_len = 2 * 8; - fadt->duty_offset = 0; - fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; -- To view, visit https://review.coreboot.org/c/coreboot/+/74438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e84c8ccd2772c9b3d61f71b74324c8d28f4eefe Gerrit-Change-Number: 74438 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Jonathan Zhang, Matt DeVillier, Johnny Lin, Tim Wawrzynczak, Christian Walter, Kyösti Mälkki, Fred Reitberger, Tim Chu. Hello build bot (Jenkins), Raul Rangel, Jonathan Zhang, Matt DeVillier, Arthur Heymans, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Fred Reitberger, Felix Held, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74430 to look at the new patch set (#2). Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields ...................................................................... ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 13 files changed, 18 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/74430/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Gerrit-Change-Number: 74430 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Nico Huber, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Naresh Solanki, Tim Chu. Hello build bot (Jenkins), Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Naresh Solanki, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74436 to look at the new patch set (#5). Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config ...................................................................... soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB that was caused by the API change in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 --- M src/soc/intel/xeon_sp/spr/cpu.c 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74436/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Nico Huber, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Naresh Solanki, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74436 ) Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74436/comment/1797844e_6a24e835 PS3, Line 8: numa > I don't understand this. Please refer to the actual change. e.g. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:12:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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