coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: cpu,soc/intel: Separate single SSDT CPU entry
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74399 ) Change subject: cpu,soc/intel: Separate single SSDT CPU entry ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74399/comment/1d85d313_ef709727 PS1, Line 422: generate_cpu_entry(device, cpu_id, core_id, num_virt); > This loop order determines UUIDs for each CPU Device(). > > Now, as long as we create a symmetrical entry for each CPU, the order does not really matter. But the UUIDs need/should sync with MADT LAPIC entries? Should the MADT order be kept inside path and generating SSDT be added to cpu ops of each lapic rather than as ops of the cpu cluster which loops over numbers? > > Is it really okay that we use the BSP CPU to create also the AP CPU's entries on some platforms? I guess it's fragile? -- To view, visit https://review.coreboot.org/c/coreboot/+/74399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Gerrit-Change-Number: 74399 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 15:29:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74436 ) Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config ...................................................................... soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB that was caused by the API change in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. This patch removes the broken API function and also adds package_id log print same as previous commit mentioned above. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74436 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/xeon_sp/spr/cpu.c 1 file changed, 22 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Sean Rhodes: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index 47873f5..2ed8e22 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -78,8 +78,9 @@ { msr_t msr; - printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n", __func__, dev_path(cpu), - cpu_index(), cpu->path.apic.apic_id); + printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, + cpu->path.apic.package_id); /* * Enable PWR_PERF_PLTFRM_OVR and PROCHOT_LOCK. @@ -275,7 +276,4 @@ if (mp_init_with_smm(bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); - - /* update numa domain for all cpu devices */ - xeonsp_init_cpu_config(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/jasperlake: Hook up GMA ACPI brightness controls
by Sean Rhodes (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74324 ) Change subject: soc/intel/jasperlake: Hook up GMA ACPI brightness controls ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa9872cd590c3b1298667cc80354ed3efd91c6c8 Gerrit-Change-Number: 74324 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 15:12:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Eric Lai (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Tim Van Patten, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: -Code-Review (1 comment) File src/vendorcode/amd/fsp/phoenix/platform_descriptors.h: https://review.coreboot.org/c/coreboot/+/74378/comment/2de57c18_eda9809c PS1, Line 194: uint32_t link_speed_capability :2; // See dxio_link_speed_cap > oh, this is a 3 bit field in agesa while it's still a 2 bit field in coreboot. […] whoops nice catch. -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Apr 2023 15:01:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Revert "soc/intel/xeon_sp: Don't sort struct device cpus for numa"
by Sean Rhodes (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jonathan Zhang, Simon Chou, Paul Menzel, Angel Pons, TangYiwei, Patrick Rudolph, Lance Zhao, Anjaneya "Reddy" Chagam, Johnny Lin, Ziang Wang, Tim Wawrzynczak, Christian Walter, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73908 ) Change subject: Revert "soc/intel/xeon_sp: Don't sort struct device cpus for numa" ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/73908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I371d9c3ab9351c1e60685e2210c9dbaaac23f09d Gerrit-Change-Number: 73908 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 15:00:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
by Sean Rhodes (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Nico Huber, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Lean Sheng Tan, Naresh Solanki, Tim Chu. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74436 ) Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 15:00:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/lenovo/x200: Configure ck505 clockgen
by Swift Geek (Sebastian Grzywna) (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Arthur Heymans, Alexander Couzens. Swift Geek (Sebastian Grzywna) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74418 ) Change subject: mb/lenovo/x200: Configure ck505 clockgen ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: This is probably not the best commit to enable AMT setup (sticky bit 4, at byte 0) Also it tries to write over vendor IDs and other readonly fields -- To view, visit https://review.coreboot.org/c/coreboot/+/74418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9bbbaed43b74e8782f6963e491dbfa3b8b5247 Gerrit-Change-Number: 74418 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Fri, 14 Apr 2023 14:51:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case
by Felix Held (Code Review) 14 Apr '23

14 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74375 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case ...................................................................... vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be selected. This causes vc/google/chromeec/acpi/chromeos.asl to be included in the DSDT and chromeos_acpi_gpio_generate to be called when generating the coreboot SSDT. When a mainboard also uses DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0 and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only checked if the GPIO table was non-NULL, which caused the function to exit early and not generate the OIPG package which causes the kernel to complain about referencing the non-existing OIPG package. To avoid this, only exit in the GPIO table pointer being NULL case if the number of GPIOs is non-0. TEST=Error about missing OIPG ACPI object in dmesg disappears on birman. Before: [ 0.241339] chromeos_acpi: registering CHSW 0 [ 0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330) [ 0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531) [ 0.241933] chromeos_acpi: failed to retrieve GPIO (5) [ 0.242011] chromeos_acpi: registering VBNV 0 [ 0.242113] chromeos_acpi: registering VBNV 1 [ 0.242284] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.242462] chromeos_acpi: installed With the patch applied: [ 0.242580] chromeos_acpi: registering CHSW 0 [ 0.242714] chromeos_acpi: registering VBNV 0 [ 0.242817] chromeos_acpi: registering VBNV 1 [ 0.242990] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.243249] chromeos_acpi: installed Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74375 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/google/chromeos/acpi.c 1 file changed, 48 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 801f33d..fb6d0a5 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -14,7 +14,7 @@ num = variant_cros_gpio.count; gpios = variant_cros_gpio.gpios; - if (!gpios) + if (num && !gpios) return; acpigen_write_scope("\\"); -- To view, visit https://review.coreboot.org/c/coreboot/+/74375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 Gerrit-Change-Number: 74375 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74377 ) Change subject: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM) ...................................................................... soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM) This patch avoids cannonlake base config to select eNEM for CAR by default. Rather allow other SoC config to choose the applicable CAR mode between eNEM and NEM. CML and WHL select eNEM whereas CFL decided to use NEM for CAR setup. Here is some background about why CFL SoC platform decided to choose NEM over eNEM: It was found that some coffeelake CPUs like Intel i3 9100E fail to enter CAR mode because some MSR used by NEM enhanced are lacking. According to the Intel SDM CPUID.EAX=07h.ECX=0 reg EBX[12 or 15] should indicate the presence of IA32_PAR_ASSOC and CPUID.EAX=10h.ECX[1 or 2] reg ECX[2] should indicate IA32_L3_QOS_CFG and IA32_L2_QOS_CFG respectively but even on a Intel coffeelake CPU that works with the NEM_ENHANCED these CPUID bits are all 0 so there is no way of knowing whether NEM_ENHANCED will work at runtime. Instead just always use regular NEM. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74377 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 34 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c4855da..33025eb 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -8,6 +8,7 @@ select HAVE_EXP_X86_64_SUPPORT select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM + select INTEL_CAR_NEM select SOC_INTEL_CONFIGURE_DDI_A_4_LANES config SOC_INTEL_WHISKEYLAKE @@ -16,6 +17,7 @@ select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM + select INTEL_CAR_NEM_ENHANCED select SOC_INTEL_CONFIGURE_DDI_A_4_LANES config SOC_INTEL_COMETLAKE @@ -23,6 +25,7 @@ select SOC_INTEL_CANNONLAKE_BASE select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO + select INTEL_CAR_NEM_ENHANCED select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC @@ -71,7 +74,6 @@ select HAVE_HYPERTHREADING select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM_ENHANCED select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP -- To view, visit https://review.coreboot.org/c/coreboot/+/74377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Gerrit-Change-Number: 74377 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74377 ) Change subject: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM) ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Gerrit-Change-Number: 74377 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 14:44:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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2015

2014

2013

coreboot-gerrit April 2023