coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Tim Van Patten (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... Patch Set 6: Code-Review+2 (1 comment) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/74334/comment/3efbe965_fcb8b674 PS6, Line 242: mem_pool_free(&cbfs_cache, mapping); > > This will attempt to free &mdev->base[offset] if mem_pool_alloc() failed initially. […] Can you open a tech-debt bug to address that memory leak? It would be good to not lose track of it, since 86Kb is 1/3 of the total cache size (assuming there is a limit on how large the cache can be, rather than just growing it whenever it fills up). Admittedly, I'm not sure if cleaning it up is worth the extra complication that would be required to handle freeing/reallocating in the middle. -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Apr 2023 17:00:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/hades: move PCIEXP_SUPPORT_RESIZABLE_BARS to common
by Nick Vaccaro (Code Review) 14 Apr '23

14 Apr '23

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74371 ) Change subject: mb/google/hades: move PCIEXP_SUPPORT_RESIZABLE_BARS to common ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8618f2da3133c6b52427375c55a69d7014c4881 Gerrit-Change-Number: 74371 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 16:59:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Karthik Ramasubramanian (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/74334/comment/b4328c60_92538aab PS6, Line 242: mem_pool_free(&cbfs_cache, mapping); > This will attempt to free &mdev->base[offset] if mem_pool_alloc() failed initially. However, looking at the implementation of mem_pool_free() , mp->last_alloc will not point to that address, so it will return early and do nothing. Yes, your understanding is correct. From our use-case, the only time we encounter this scenario is when the code could not perform mem_pool_alloc successfully. In that scenario, it does not hurt to call mem_pool_free since it will return early. > Looking at the implementation of mem_pool.c , it expects cached blocks to be returned in the order they are allocated. Otherwise, the memory is lost forever, which seems like the most likely case without careful consideration of allocations/frees. mem_pool library supports nested allocation up to the depth of 2(last_alloc, second_to_last_alloc). Beyond that, you can still allocate. But the library will start losing track of buffers already allocated. > How much space is left in the CBFS cache with this change? We start with CBFS_CACHE of 256 KiB. Also we are enabling it with this change. Based on inspection of one of Raul's comments earlier, there seems to be a leak of 86 KB. Even with the leak we are still able to accommodate all our use-cases. These are the files where the leak is observed and can be investigated as follow-up CLs. [DEBUG] FMAP: area RO_VPD found @ 800000 (16384 bytes) [SPEW ] spi_dma_readat_dma: start: dest: 0x02181600, source: 0x800000, size: 16384 -- [INFO ] CBFS: Found 'pci1002,1506.rom' @0x93500 size 0xae00 in mcache @0xb877c380 [SPEW ] spi_dma_readat_dma: start: dest: 0x02187600, source: 0xb3580, size: 44544 -- [INFO ] CBFS: Found 'cpu_microcode_8a00.bin' @0x9e380 size 0xc80 in mcache @0xb877c400 [SPEW ] spi_dma_readat_dma: start: dest: 0x02192400, source: 0xbe400, size: 3200 -- [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x5f680 size 0x4527 in mcache @0xb877c200 [SPEW ] spi_dma_readat_dma: start: dest: 0x02193080, source: 0x7f700, size: 17703 -- [INFO ] Couldn't obtain OEM name from CBI [SPEW ] spi_dma_readat_dma: start: dest: 0x021975c0, source: 0x61e000, size: 4096 -- [INFO ] CBFS: Found 'fallback/payload' @0xc4a80 size 0x2811c in mcache @0xb877c6d8 [SPEW ] spi_dma_readat_dma: start: dest: 0x021985c0, source: 0xe4b00, size: 164124 -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Apr 2023 16:50:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable all DDI lanes
by Anil Kumar K (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74413 ) Change subject: mb/google/rex: Enable all DDI lanes ...................................................................... Patch Set 6: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74413/comment/55447f01_04e7b7f6 PS4, Line 9: tunneled : display > Do you mean “DisplayPort tunneling”? Ack https://review.coreboot.org/c/coreboot/+/74413/comment/5c3edaac_d02d0019 PS4, Line 12: Branch=None > Please add BUG=b:273901499 Done https://review.coreboot.org/c/coreboot/+/74413/comment/3d38681f_84032c4b PS4, Line 12: Branch=None > don't need, please drop Done https://review.coreboot.org/c/coreboot/+/74413/comment/dd702f6b_e9817bf9 PS4, Line 13: Test > TEST Done https://review.coreboot.org/c/coreboot/+/74413/comment/807ac04e_e11d0287 PS4, Line 13: rex > google/rex Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Gerrit-Change-Number: 74413 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: srinivas.kulkarni(a)intel.com Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 14 Apr 2023 16:32:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable all DDI lanes
by Anil Kumar K (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74413 to look at the new patch set (#6). Change subject: mb/google/rex: Enable all DDI lanes ...................................................................... mb/google/rex: Enable all DDI lanes This patch enables all DDI ports on Rex board to support display port tunneling and dual display on TBT dock. BUG=b:273901499 TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74413/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Gerrit-Change-Number: 74413 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: srinivas.kulkarni(a)intel.com Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Enable all DDI lanes
by Anil Kumar K (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74413 to look at the new patch set (#5). Change subject: mb/google/rex: Enable all DDI lanes ...................................................................... mb/google/rex: Enable all DDI lanes This patch enables all DDI ports on Rex board to support display port tunneling and dual display on TBT dock. BUG=b:273901499 TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74413/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Gerrit-Change-Number: 74413 Gerrit-PatchSet: 5 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: srinivas.kulkarni(a)intel.com Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/speedstep: Separate single SSDT CPU entry
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74400 ) Change subject: cpu/intel/speedstep: Separate single SSDT CPU entry ...................................................................... Patch Set 3: (1 comment) File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/c/coreboot/+/74400/comment/394e5071_c8455b61 PS3, Line 107: ac > acpigen_write_processor_device_end() ? No, did not change to Device() yet with this commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/74400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Gerrit-Change-Number: 74400 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 14 Apr 2023 16:15:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu,soc/intel: Separate single SSDT CPU entry
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74399 ) Change subject: cpu,soc/intel: Separate single SSDT CPU entry ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74399/comment/da865048_88bb4153 PS1, Line 422: generate_cpu_entry(device, cpu_id, core_id, num_virt); > > This loop order determines UUIDs for each CPU Device(). > > > > Now, as long as we create a symmetrical entry for each CPU, the order does not really matter. But the UUIDs need/should sync with MADT LAPIC entries? > > Should the MADT order be kept inside path and generating SSDT be added to cpu ops of each lapic rather than as ops of the cpu cluster which loops over numbers? > I thought of sorting cpu->sibling the way we want them to appear in MADT and have the UUID determined inside device object, possibly path. I have already prepares something towards that direction, which also explains the spurious passing of *device in this patchset. And yes, some fill_ssdt ops would move around. > > Is it really okay that we use the BSP CPU to create also the AP CPU's entries on some platforms? > > I guess it's fragile? -- To view, visit https://review.coreboot.org/c/coreboot/+/74399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Gerrit-Change-Number: 74399 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 14 Apr 2023 16:14:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Felix Singer, Sean Rhodes, Tarun Tuli, Nico Huber, Subrata Banik, Christian Walter, Angel Pons, Michael Niewöhner. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74403 ) Change subject: soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Gerrit-Change-Number: 74403 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 14 Apr 2023 15:59:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update fsp submodule to upstream master
by build bot (Jenkins) (Code Review) 14 Apr '23

14 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74442 ) Change subject: Update fsp submodule to upstream master ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174203): https://review.coreboot.org/c/coreboot/+/74442/comment/fc21d27d_bbf027b5 PS1, Line 9: Updating from commit id 6f2f17f: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88d954568b427ea288610710155014ae0f460ff9 Gerrit-Change-Number: 74442 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Apr 2023 15:39:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023