coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Christian Walter, Shuming Chu (Shuming), Lean Sheng Tan. Arthur Heymans has uploaded a new patch set (#6) to the change originally created by Shuming Chu (Shuming). ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time ...................................................................... soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time Set up a postcar MTRR solution that caches the full DRAM including TSEG. FSP-S uses memory above cbmem_top and below TSEG base. Caching that region dramatically improves boottimes. TESTED on Archer City 2S: Boot time goes from ~19m to ~4m. Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M src/soc/intel/xeon_sp/memmap.c 1 file changed, 24 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/71085/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 6 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Johnny Lin, Paul Menzel, Christian Walter, Shuming Chu (Shuming), Lean Sheng Tan. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71085/comment/26d61c6d_23866247 PS2, Line 7: boottime > boot time Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 5 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:37:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Johnny Lin, Paul Menzel, Christian Walter, Shuming Chu (Shuming). Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71085/comment/7402baa1_c0b34f47 PS4, Line 13: TESTED on Archer City 2S: Boottime goes from ~19m to ~4m. > Minutes or seconds? ;-) m stands for minutes here :-) 19m is indeed a very long time: running things from uncached DRAM has a big performance impact... -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 5 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:36:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/tigerlake: Enable early caching of RAMTOP region
by Sean Rhodes (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73738 ) Change subject: soc/intel/tigerlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Gerrit-Change-Number: 73738 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:35:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Sean Rhodes (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Maximilian Brune, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73736 ) Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 8 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:35:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Johnny Lin, Paul Menzel, Christian Walter, Shuming Chu (Shuming). Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71085/comment/693bb016_b7b376fc PS4, Line 7: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/71085/comment/4a8fb5fa_515119e8 PS4, Line 12: > Maybe paste the MTRR before and after for easy comparison? The patch was made 18 months ago iirc. Sorry I don't have those available anymore. I think TSEG top was pretty well aligned so not so many MTRR were needed but I can't confirm this. -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 4 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:35:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
by Arthur Heymans (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Johnny Lin, Paul Menzel, Christian Walter, Shuming Chu (Shuming). Arthur Heymans has uploaded a new patch set (#5) to the change originally created by Shuming Chu (Shuming). ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time ...................................................................... soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time Set up a postcar MTRR solution that caches the full DRAM including TSEG. FSP-S uses memory above cbmem_top and below TSEG base. Caching that region dramatically improves boottimes. TESTED on Archer City 2S: Boottime goes from ~19m to ~4m. Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M src/soc/intel/xeon_sp/memmap.c 1 file changed, 24 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/71085/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 5 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Nico Huber, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Naresh Solanki, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74436 ) Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/xeon_sp/spr/cpu.c: https://review.coreboot.org/c/coreboot/+/74436/comment/9ec384d1_f8d0fd89 PS3, Line 83: cpu->path.apic.package_id); > The commit message should match the changes. Please either update the commit […] Is that ok? -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:23:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
by Lean Sheng Tan (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Lean Sheng Tan, Naresh Solanki, Tim Chu. Hello build bot (Jenkins), Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Naresh Solanki, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74436 to look at the new patch set (#6). Change subject: soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config ...................................................................... soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB that was caused by the API change in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. This patch removes the broken API function and also adds package_id log print same as previous commit mentioned above. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 --- M src/soc/intel/xeon_sp/spr/cpu.c 1 file changed, 18 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74436/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Gerrit-Change-Number: 74436 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
by Kyösti Mälkki (Code Review) 14 Apr '23

14 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Jonathan Zhang, Matt DeVillier, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Fred Reitberger, Tim Chu. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74430 ) Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/stoneyridge/acpi.c: https://review.coreboot.org/c/coreboot/+/74430/comment/1dc1c9cb_840510b6 PS2, Line 78: fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ Felix, do you think this would require a CPU _PTC to work? After Processor() was dropped P_BLK/P_CNT address was lost? -- To view, visit https://review.coreboot.org/c/coreboot/+/74430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Gerrit-Change-Number: 74430 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Apr 2023 13:21:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023