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Change subject: cpu,soc/intel: Sync ACPI CPU object implementations
......................................................................
Patch Set 2: Code-Review+2
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Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
......................................................................
Patch Set 1: -Code-Review
(1 comment)
File src/vendorcode/amd/fsp/phoenix/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/74378/comment/2e66b59e_7a562cac
PS1, Line 194: uint32_t link_speed_capability :2; // See dxio_link_speed_cap
using GEN4 enum value overflows this field
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Change subject: cpu,soc/intel: Use acpigen_write_processor_device()
......................................................................
Patch Set 9: Code-Review+2
(2 comments)
File src/cpu/intel/speedstep/acpi.c:
https://review.coreboot.org/c/coreboot/+/72488/comment/f9e64fdf_1332a6d8
PS4, Line 80: int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
> the i/o port based c state entry can also be done with acpigen_write_processor_device, so you can re […]
the part this was about was taken out of the patch, so i'll mark this as resolved
File src/southbridge/intel/i82371eb/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/72488/comment/da808252_6860034a
PS3, Line 31: acpigen_write_processor_device(cpu);
> in that case, the processor objects are defined in the dsdt and without having looked at the code i' […]
this part was taken out of the patch, so i'll mark this as resolved
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Hello Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for numa
......................................................................
soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for
numa
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB
that was caused by commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6
---
M src/soc/intel/xeon_sp/spr/cpu.c
1 file changed, 17 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74436/3
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Change subject: Revert "soc/intel/xeon_sp: Don't sort struct device cpus for numa"
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Hello Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu,
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to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for numa
......................................................................
soc/intel/xeon_sp/spr: Add support to not sort struct device cpus for
numa
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB
that was caused by commit:36e6f9bc047f86e1628c8c41d3ac16d80fb344de.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6
---
M src/soc/intel/xeon_sp/spr/cpu.c
1 file changed, 17 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74436/2
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Change subject: sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines
......................................................................
Patch Set 1: Code-Review+2
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Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
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Change subject: Revert "soc/intel/xeon_sp: Don't sort struct device cpus for numa"
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