coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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5761 discussions

[M] Change in coreboot[master]: soc/intel/cmn/cse: Store ISH firmware version into CBMEM
by Kangheui Won (Code Review) 15 Apr '23

15 Apr '23

1 0

[L] Change in coreboot[master]: [RFC] drivers/option: Add option list in cbtable
by Benjamin Doron (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Angel Pons, Maximilian Brune. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74121 ) Change subject: [RFC] drivers/option: Add option list in cbtable ...................................................................... Patch Set 1: (1 comment) File src/drivers/option/cfr.h: https://review.coreboot.org/c/coreboot/+/74121/comment/d0bcbcec_527e9aa2 PS1, Line 71: /* struct cfr_string opt_name; */ : /* struct cfr_string ui_name; */ : /* struct lb_cfr_enum_value enum_values[]; */ > Might have a problem parsing these variable length fields because the length field of a `cfr_string` […] Ah, possibly 'string length' and 'actual length' fields? I think it's fine though: just need to align the pointer after walking over an individual `cfr_string`. -- To view, visit https://review.coreboot.org/c/coreboot/+/74121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 05:28:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [RFC] drivers/option: Add option list in cbtable
by Benjamin Doron (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Angel Pons, Maximilian Brune. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74121 ) Change subject: [RFC] drivers/option: Add option list in cbtable ...................................................................... Patch Set 1: (1 comment) File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/74121/comment/8e08ded2_028c3be0 PS1, Line 127: write_body(header); : : menu->size = sm_compute_record_size((char *)menu, header); A thought: if we let the boot-state machine do this, then silicon, platform drivers, board code, etc can all add their options. `sm_write_cfr()` gets split in two and removed from the API for this. My in-progress implementation for EDK2 should handle cases where the user enabled the driver but nothing adds forms: we process the header and `while (ProcessedLength < CbCfrSetupMenu->size) { .. }` exits early, so no forms are produced, meaning the menu (in theory) is empty. -- To view, visit https://review.coreboot.org/c/coreboot/+/74121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 05:23:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/baytrail: Make acpi_madt_irq_overrides() static
by Kyösti Mälkki (Code Review) 15 Apr '23

15 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74325 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/baytrail: Make acpi_madt_irq_overrides() static ...................................................................... soc/intel/baytrail: Make acpi_madt_irq_overrides() static Change-Id: Id362e023358054df2c4511fd108c313da868306d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74325 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/include/soc/acpi.h 2 files changed, 25 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 77bdcc9..8bfb345 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -85,16 +85,6 @@ return sci_irq; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - current = acpi_madt_irq_overrides(current); - - return current; -} - static acpi_tstate_t soc_tss_table[] = { { 100, 1000, 0, 0x00, 0 }, { 88, 875, 0, 0x1e, 0 }, @@ -286,7 +276,7 @@ acpigen_write_processor_cnot(pattrs->num_cpus); } -unsigned long acpi_madt_irq_overrides(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci_irq = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; @@ -306,3 +296,13 @@ return current; } + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* IOAPIC */ + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index d629b24..b747db7 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -6,6 +6,5 @@ #include <acpi/acpi.h> int acpi_sci_irq(void); -unsigned long acpi_madt_irq_overrides(unsigned long current); #endif /* _BAYTRAIL_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id362e023358054df2c4511fd108c313da868306d Gerrit-Change-Number: 74325 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
by Kyösti Mälkki (Code Review) 15 Apr '23

15 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74316 ) Change subject: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC ...................................................................... sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. For asus/p2b, this adds MADT LAPIC entries, even though platform has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates the MADT, including an entry for LAPIC address. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/madt.c M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/lynxpoint/Kconfig 33 files changed, 46 insertions(+), 51 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Felix Held: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index ec7fcc4..5af8b22 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -31,6 +31,9 @@ Set to indicate <soc/nvs.h> exists for the platform with a definition for global_nvs. +config ACPI_COMMON_MADT_LAPIC + bool + config ACPI_NO_MADT bool help diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index de5abe0..492d043 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -312,6 +312,9 @@ if (CONFIG(ACPI_HAVE_PCAT_8259)) madt->flags |= 1; + if (CONFIG(ACPI_COMMON_MADT_LAPIC)) + current = acpi_create_madt_lapics_with_nmis(current); + if (!CONFIG(ACPI_NO_MADT)) current = acpi_fill_madt(current); diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 13ddb3e..ba9d3c8 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -8,8 +8,6 @@ struct device *bdev, *dev = NULL; struct resource *res = NULL; - current = acpi_create_madt_lapics_with_nmis(current); - /* Southbridge IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, 0xfec00000); diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index e6262d1..593cbc7 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -10,9 +10,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index ef240c1..e139639 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -6,9 +6,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index b8ac827..08effca 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -21,9 +21,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index fd62ad6..289efbc 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -2,6 +2,7 @@ bool depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO select ACPI_AMD_HARDWARE_SLEEP_VALUES + select ACPI_COMMON_MADT_LAPIC help Select this option to use the AcpiMmio ACPI registers. diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 49fb658..cb8039d 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -24,9 +24,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 83b24ec..17d8955 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -23,9 +23,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 8e90d44..5e37a27 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -24,9 +24,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a6f1ebd..227a5d8 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -28,9 +28,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index caa6496..947c806 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -26,9 +26,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5ecfe3e..0f908b6 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 42e4b26..77bdcc9 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -87,9 +87,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4d3d4df..8d540f3 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 9ef7a75..308da12 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -328,9 +328,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 5a80d32..63f0439 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -4,6 +4,7 @@ config PCH_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index bf5fa56..8f4e308 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -1,6 +1,7 @@ config SOC_INTEL_COMMON_BLOCK_ACPI depends on SOC_INTEL_COMMON_BLOCK_CPU depends on SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID bool help Intel Processor common code for ACPI diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 4139054..51649d0 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -87,11 +87,8 @@ size_t ioapic_entries; /* Local APICs */ - - if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + if (!CONFIG(ACPI_COMMON_MADT_LAPIC)) current = acpi_create_madt_lapics_with_nmis_hybrid(current); - else - current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ ioapic_entries = soc_get_ioapic_info(&ioapic_table); diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 53f7b3e..4b19431 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -10,6 +10,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 7fee1f1..a0d8605 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -10,6 +10,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index b85e110..2482391 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -6,9 +6,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 03e70a6..08ffb00 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,4 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 3916b41..2be911d 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801DX bool + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index b1b885b..330915f 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 69c1469..2871453 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -351,9 +351,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 4d6b097..d93afa6 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/i82801ix/madt.c b/src/southbridge/intel/i82801ix/madt.c index 009c9ea..1ac8149 100644 --- a/src/southbridge/intel/i82801ix/madt.c +++ b/src/southbridge/intel/i82801ix/madt.c @@ -6,9 +6,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b189852..62684ec 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ead2b8a..8ff7926 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -381,9 +381,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index fd5e322..ffeef5d 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -7,6 +7,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 26b1630..c5b1f0b 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -8,9 +8,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 6305812..9cea74b 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -7,6 +7,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT -- To view, visit https://review.coreboot.org/c/coreboot/+/74316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Gerrit-Change-Number: 74316 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static
by Kangheui Won (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, SRIDHAR SIRICILLA, Subrata Banik, Kapil Porwal, Dinesh Gehlot. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74388 ) Change subject: soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac Gerrit-Change-Number: 74388 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 04:43:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya: Enable CSE FPT Info config for Nissa
by Kangheui Won (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Derek Huang, Kyle Lin, Kapil Porwal, Dinesh Gehlot. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74387 ) Change subject: mb/google/brya: Enable CSE FPT Info config for Nissa ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c Gerrit-Change-Number: 74387 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 04:43:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: drivers/intel/ish: Hook get ISH version into `.final`
by Kangheui Won (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot, Paul Menzel, Sridhar Siricilla. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74209 ) Change subject: drivers/intel/ish: Hook get ISH version into `.final` ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8 Gerrit-Change-Number: 74209 Gerrit-PatchSet: 17 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 04:43:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Kangheui Won (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot, Sridhar Siricilla. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/bf35f468_3fd145bd PS7, Line 1089: : const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); : struct cse_fw_partition_info *version; : version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); : version->cur_cse_fw_version.major = cse_bp->fw_ver.major; : version->cur_cse_fw_version.minor = cse_bp->fw_ver.minor; : version->cur_cse_fw_version.hotfix = cse_bp->fw_ver.hotfix; : version->cur_cse_fw_version.build = cse_bp->fw_ver.build; : } : > Ack Sorry to catch up late, but using HECI command is intended here. We can parse BPDT and sub-partition header in CBFS (I'm already working on it) but we need another data source to compare and verify ISH version. -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 16 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 04:41:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Kangheui Won (Code Review) 15 Apr '23

15 Apr '23

1 0

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