coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add B0 stepping CPU ID
by Subrata Banik (Code Review) 15 Apr '23

15 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74300 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Add B0 stepping CPU ID ...................................................................... soc/intel/meteorlake: Add B0 stepping CPU ID This patch adds CPU ID for B0 stepping (aka ES2). DOC=#723567 TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log. Signed-off-by: Musse Abdullahi <musse.abdullahi(a)intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Signed-off-by: Musse Abdullahi <musse.abdullahi(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/meteorlake/bootblock/report_platform.c 3 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 7caafd5..2d64c5f 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -71,6 +71,7 @@ #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 +#define CPUID_METEORLAKE_B0 0xa06a2 #define CPUID_RAPTORLAKE_P_J0 0xb06a2 #define CPUID_RAPTORLAKE_P_Q0 0xb06a3 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 6689047..7466ff6 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -34,6 +34,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index a5d32f3..3e8bc56 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -19,6 +19,7 @@ } cpu_table[] = { { CPUID_METEORLAKE_A0_1, "MeteorLake A0" }, { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, + { CPUID_METEORLAKE_B0, "MeteorLake B0" }, }; static struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/74300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Gerrit-Change-Number: 74300 Gerrit-PatchSet: 5 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Subrata Banik (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Paul Menzel, Dinesh Gehlot, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74255 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/74255/comment/6081f7f1_508c7fb2 PS9, Line 56: > > > > … from payload or OS, as that information can only be retrieved in the firmware stage(?) due to security measures(?). > > > > > > I don't think so, cbmem id can be retrieve from os (in read-only format) > > > > > > cbmem -r <cbmem_id> > > > > marking this resolve now. please feel free share the thoughts otherwise. > > I guess reporting to the OS is not the intended purpose here, but just in case: coreboot tables would be better. cbmem is just an internal database structure that the payload or OS should not know anything about in principle. for now, we will be able to receive the ISH version from `cbmem -c` itself -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 15 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Apr 2023 12:09:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Store ISH firmware version into CBMEM
by Subrata Banik (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74208 ) Change subject: soc/intel/cmn/cse: Store ISH firmware version into CBMEM ...................................................................... Patch Set 20: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74208/comment/5c5f7e97_3fb742a4 PS20, Line 1246: This API can only be executed after memory has been initialized. > Make this explicit in code? i hope u are asking to add ENV_RAMSTAGE check inside the code? -- To view, visit https://review.coreboot.org/c/coreboot/+/74208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Gerrit-Change-Number: 74208 Gerrit-PatchSet: 20 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Apr 2023 12:08:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/8215a7d8_a965799e PS16, Line 1250: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) { : timestamp_add_now(TS_CSE_FW_SYNC_START); : cse_fw_sync(); : timestamp_add_now(TS_CSE_FW_SYNC_END); : : if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) : store_cse_rw_fw_version(); : } : } > The codeflow is quite confusing... Can't you add store_cse_rw_fw_version in the same function call? Those functions for SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE and SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE look close to identical why function call ? inside cse_fw_sync? -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 16 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Apr 2023 12:07:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add B0 stepping CPU ID
by Eric Lai (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Jamie Ryu, Paul Menzel, Musse Abdullahi. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74300 ) Change subject: soc/intel/meteorlake: Add B0 stepping CPU ID ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Gerrit-Change-Number: 74300 Gerrit-PatchSet: 3 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-Attention: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 11:20:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/variants/hades: Update GPIO configs
by Eric Lai (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73909 ) Change subject: mb/google/brya/variants/hades: Update GPIO configs ...................................................................... Patch Set 7: Code-Review+2 (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/73909/comment/72d70e3b_bfb2ab90 PS7, Line 178: default 20 if BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_20 (GPP_A20_IRQ) Can this override by Kconfig.name? I am not sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/73909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d Gerrit-Change-Number: 73909 Gerrit-PatchSet: 7 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 11:19:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add B0 stepping CPU ID
by Kapil Porwal (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Jamie Ryu, Paul Menzel, Musse Abdullahi. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74300 ) Change subject: soc/intel/meteorlake: Add B0 stepping CPU ID ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Gerrit-Change-Number: 74300 Gerrit-PatchSet: 3 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-Attention: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 10:27:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/variants/hades: Update GPIO configs
by Tarun Tuli (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Nick Vaccaro, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73909 ) Change subject: mb/google/brya/variants/hades: Update GPIO configs ...................................................................... Patch Set 7: (1 comment) Patchset: PS6: > We should update the device tree and Kconfig for TPM IRQ. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d Gerrit-Change-Number: 73909 Gerrit-PatchSet: 7 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 10:17:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu,soc/intel: Separate single SSDT CPU entry
by Kyösti Mälkki (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74399 ) Change subject: cpu,soc/intel: Separate single SSDT CPU entry ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74399/comment/c55efc17_69da8d54 PS1, Line 390: const struct device *device, > unused? Done https://review.coreboot.org/c/coreboot/+/74399/comment/285ea19e_bb7d4c63 PS1, Line 422: generate_cpu_entry(device, cpu_id, core_id, num_virt); > > > Is it really okay that we use the BSP CPU to create also the AP CPU's entries on some platforms? > > > > I guess it's fragile? Well.. That sounds like a major rewrite if that has to change for some model. -- To view, visit https://review.coreboot.org/c/coreboot/+/74399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Gerrit-Change-Number: 74399 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Apr 2023 10:03:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Arthur Heymans (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Subrata Banik, Paul Menzel, Dinesh Gehlot. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74255 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... Patch Set 15: (2 comments) Patchset: PS15: > > Can you squash the commit adding a Kconfig with the one doing something with it? > > i believe you are suggesting to add this kconfig with CB:74256 yes please :-) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/74255/comment/4e40e25c_e75cb90b PS9, Line 56: > > > … from payload or OS, as that information can only be retrieved in the firmware stage(?) due to security measures(?). > > > > I don't think so, cbmem id can be retrieve from os (in read-only format) > > > > cbmem -r <cbmem_id> > > marking this resolve now. please feel free share the thoughts otherwise. I guess reporting to the OS is not the intended purpose here, but just in case: coreboot tables would be better. cbmem is just an internal database structure that the payload or OS should not know anything about in principle. -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 15 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 09:37:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit April 2023