coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: Update vboot submodule to upstream main
by Lean Sheng Tan (Code Review) 15 Apr '23

15 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74401 ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id 5b8596ce: 2sha256_arm: Fix data abort issue to commit id 35f50c31: Fix build error when compiling without -DNDEBUG This brings in 41 new commits. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I58f6740c34670ea5a501ff2ee8cfcf9d2a1c25e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74401 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M 3rdparty/vboot 1 file changed, 23 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index 5b8596c..35f50c3 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 5b8596cefd1a61252501943f2534323708338732 +Subproject commit 35f50c3154e58821cc027bf13be2b949bc4c90f3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58f6740c34670ea5a501ff2ee8cfcf9d2a1c25e9 Gerrit-Change-Number: 74401 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: [do not merge] mb/prodrive/atlas: for testing
by Lean Sheng Tan (Code Review) 15 Apr '23

15 Apr '23

Lean Sheng Tan has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/67415 ) Change subject: [do not merge] mb/prodrive/atlas: for testing ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/67415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c686aacea130c99e8ab2fe984b150a7ad6f82d Gerrit-Change-Number: 67415 Gerrit-PatchSet: 16 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
by Lean Sheng Tan (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Johnny Lin, Paul Menzel, Christian Walter, Arthur Heymans, Shuming Chu (Shuming). Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 ) Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time ...................................................................... Patch Set 6: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/71085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7 Gerrit-Change-Number: 71085 Gerrit-PatchSet: 6 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 14:38:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/tigerlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 15 Apr '23

15 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73738 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/tigerlake: Enable early caching of RAMTOP region ...................................................................... soc/intel/tigerlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fca4f79..9928591 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -93,7 +93,8 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE - select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 select X86_CLFLUSH_CAR -- To view, visit https://review.coreboot.org/c/coreboot/+/73738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Gerrit-Change-Number: 73738 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Lean Sheng Tan (Code Review) 15 Apr '23

15 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73736 ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... soc/intel/alderlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot Starlab ADL laptop to OS. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73736 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 31 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved Subrata Banik: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 480ee0b..0913480 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -83,6 +83,8 @@ select SOC_INTEL_COMMON select CPU_INTEL_COMMON_VOLTAGE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC @@ -118,7 +120,6 @@ select SOC_INTEL_COMMON_BLOCK_VTD select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG - select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 10 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Enable early caching of RAMTOP region
by Maximilian Brune (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Lean Sheng Tan. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73736 ) Change subject: soc/intel/alderlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Gerrit-Change-Number: 73736 Gerrit-PatchSet: 9 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 14:33:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add B0 stepping CPU ID
by Subrata Banik (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Musse Abdullahi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74300 ) Change subject: soc/intel/meteorlake: Add B0 stepping CPU ID ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74300/comment/8fe0aa91_fbeefc13 PS4, Line 14: Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 > Duplicate signature Please fix please take care of this from next time onwards. -- To view, visit https://review.coreboot.org/c/coreboot/+/74300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Gerrit-Change-Number: 74300 Gerrit-PatchSet: 5 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-Attention: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 12:18:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/59672011_8ed82308 PS16, Line 1250: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) { : timestamp_add_now(TS_CSE_FW_SYNC_START); : cse_fw_sync(); : timestamp_add_now(TS_CSE_FW_SYNC_END); : : if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) : store_cse_rw_fw_version(); : } : } > > > The codeflow is quite confusing... Can't you add store_cse_rw_fw_version in the same function call? Those functions for SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE and SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE look close to identical > > > > why function call ? inside cse_fw_sync? > > *which the major dependency to store the cse fw version is cse_fw_sync, which has to be performed prior to the store operation hence, used different boot state machine callbacks for cse_fw_sync at romstage, we can store it any where post that stage (after cbmem is online). for cse_fw_sync at ramstage, i have stored immediately after performing the sync operation. -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 16 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Apr 2023 12:17:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 15 Apr '23

15 Apr '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/76d88323_43afee8b PS16, Line 1250: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) { : timestamp_add_now(TS_CSE_FW_SYNC_START); : cse_fw_sync(); : timestamp_add_now(TS_CSE_FW_SYNC_END); : : if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) : store_cse_rw_fw_version(); : } : } > > The codeflow is quite confusing... Can't you add store_cse_rw_fw_version in the same function call? Those functions for SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE and SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE look close to identical > > why function call ? inside cse_fw_sync? *which -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 16 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Apr 2023 12:10:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add B0 stepping CPU ID
by build bot (Jenkins) (Code Review) 15 Apr '23

15 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74300 ) Change subject: soc/intel/meteorlake: Add B0 stepping CPU ID ...................................................................... Patch Set 4: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174228): https://review.coreboot.org/c/coreboot/+/74300/comment/0c8572f4_16704239 PS4, Line 14: Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Duplicate signature -- To view, visit https://review.coreboot.org/c/coreboot/+/74300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Gerrit-Change-Number: 74300 Gerrit-PatchSet: 4 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Sat, 15 Apr 2023 12:10:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023