coreboot-gerrit April 2023

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[L] Change in coreboot[master]: drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)
by Jan Samek (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Paul Menzel, Mario Scheithauer, Lean Sheng Tan, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74433 ) Change subject: drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp) ...................................................................... Patch Set 12: (6 comments) File src/drivers/i2c/pi608gp/pi608gp.h: https://review.coreboot.org/c/coreboot/+/74433/comment/c0497a40_9575ce10 PS12, Line 10: #define DEEMPH_LVL_MV(_LVL, _LVL_10) {.lvl = _LVL, .lvl_10 = _LVL_10} > Add spaces after { and before }? Done File src/drivers/i2c/pi608gp/pi608gp.c: https://review.coreboot.org/c/coreboot/+/74433/comment/a6ad36b5_e2f5c282 PS12, Line 17: /* Only some of the available registers are implemented. : For a full list, see the PI7C9X2G608GP datasheet. */ > As it’s not in a function body you could use: […] Done https://review.coreboot.org/c/coreboot/+/74433/comment/f5de48c0_1d8adccf PS12, Line 26: level > Add the unit to the name? Done https://review.coreboot.org/c/coreboot/+/74433/comment/e0ac379c_1237578c PS12, Line 48: { 0, 0} > Use spaces consistently? I would like to keep the numbers aligned, as it reads better and can be easier compared with the table in the datasheet. This is quite a special case as the numbers can be read as decimals. https://review.coreboot.org/c/coreboot/+/74433/comment/a931928c_9d0ef3b7 PS12, Line 54: uint8_t > Please use int [1]? […] Done https://review.coreboot.org/c/coreboot/+/74433/comment/a5ad2d69_0fb1ba7a PS12, Line 71: /* Compose the SMBus message for register read init operation (from MSB to LSB): : Byte 1: 7:3 = Rsvd., 2:0 = Command, : Byte 2: 7:4 = Rsvd., 3:0 = Port Select[4:1], : Byte 3: 7 = Port Select[0], 6 = Rsvd., 5:2 = Byte Enable, 1:0 = Reg. Addr. [11:10], : Byte 4: 7:0 = Reg. Addr.[9:2] (Reg. Addr. [1:0] fixed to 0). */ > Maybe use non-concise form? Can you please elaborate, e.g. what could be added? -- To view, visit https://review.coreboot.org/c/coreboot/+/74433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id191c4e97b99da58efd3ba38bf8cca3603ece4d5 Gerrit-Change-Number: 74433 Gerrit-PatchSet: 12 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 07:29:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)
by build bot (Jenkins) (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Mario Scheithauer, Lean Sheng Tan, Werner Zeh, Jan Samek. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74433 ) Change subject: drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp) ...................................................................... Patch Set 13: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174888): https://review.coreboot.org/c/coreboot/+/74433/comment/2a6701d1_58b29130 PS13, Line 29: Link to the datasheet: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id191c4e97b99da58efd3ba38bf8cca3603ece4d5 Gerrit-Change-Number: 74433 Gerrit-PatchSet: 13 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 07:29:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)
by Jan Samek (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Mario Scheithauer, Lean Sheng Tan, Werner Zeh, Jan Samek. Hello build bot (Jenkins), Mario Scheithauer, Arthur Heymans, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74433 to look at the new patch set (#13). Change subject: drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp) ...................................................................... drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp) This patch adds some of the variety of configuration options exported by the Pericom Inc. PI7C9X2G608GP PCIe switch over its SMBus interface. Currently implemented options are only used to adjust the switch upstream port amplitude and de-emphasis levels in millivolts. Only values specified in the switch datasheet (in tables 6-6 and 6-8) are allowed. Example of a devicetree.cb entry: chip drivers/i2c/pi608gp register "gen2_3p5_enable" = "true" register "gen2_3p5_amp" = "AMP_LVL_MV(425)" register "gen2_3p5_deemph" = \ "DEEMPH_LVL_MV(37, 5)" device i2c 0x6f on ops pi608gp_ops end end Link to the datasheet: https://web.archive.org/web/20210225074853/https://www.diodes.com/assets/Da… BUG=none TEST=Create devicetree.cb and Kconfig entries for this driver in a mainboard containing the switch and verify, that the values read out from the switch config space match the values programmed over the SMBus. Change-Id: Id191c4e97b99da58efd3ba38bf8cca3603ece4d5 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- A src/drivers/i2c/pi608gp/Kconfig A src/drivers/i2c/pi608gp/Makefile.inc A src/drivers/i2c/pi608gp/chip.h A src/drivers/i2c/pi608gp/pi608gp.c A src/drivers/i2c/pi608gp/pi608gp.h 5 files changed, 255 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/74433/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id191c4e97b99da58efd3ba38bf8cca3603ece4d5 Gerrit-Change-Number: 74433 Gerrit-PatchSet: 13 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/spi: Mmap 32M/64M flash
by Arthur Heymans (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74260 ) Change subject: soc/amd/spi: Mmap 32M/64M flash ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Wouldn't it be easier to run in 64bit mode with an adequate pt and use the full continuous region mapped in the ROM3 region? That avoids dealing with these 16M pages. -- To view, visit https://review.coreboot.org/c/coreboot/+/74260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Gerrit-Change-Number: 74260 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Apr 2023 07:23:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Disable Tccold Handshake
by Eric Lai (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Tarun Tuli, Dtrain Hsu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74737 ) Change subject: mb/google/brya/var/omnigul: Disable Tccold Handshake ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74737/comment/6ceed872_67529412 PS3, Line 13: BUG=b: miss number here. -- To view, visit https://review.coreboot.org/c/coreboot/+/74737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Gerrit-Change-Number: 74737 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 07:22:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/taeko:Disable C1E for RPL CPU
by Joey Peng (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74727 to look at the new patch set (#2). Change subject: mb/google/brya/var/taeko:Disable C1E for RPL CPU ...................................................................... mb/google/brya/var/taeko:Disable C1E for RPL CPU Disable C1E on RPL CPU for improving acoustic noise tests We would use fw_config bit 18 to identify if the CPU is ADL or RPL BUG=b:278654939 TEST:emerge-brya coreboot and check that C1E can be disabled on RPL SKU Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko/variant.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 4 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74727/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/vat/taeko:Disable C1E for RPL CPU
by build bot (Jenkins) (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: mb/google/brya/vat/taeko:Disable C1E for RPL CPU ...................................................................... Patch Set 1: (7 comments) File src/mainboard/google/brya/variants/taeko/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174886): https://review.coreboot.org/c/coreboot/+/74727/comment/de7ef190_440b0e20 PS1, Line 15: // Disable C1E for Tabor code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174886): https://review.coreboot.org/c/coreboot/+/74727/comment/4a5a0e1f_c83f6153 PS1, Line 16: if (fw_config_probe(FW_CONFIG(RPL, IS_RPL))) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174886): https://review.coreboot.org/c/coreboot/+/74727/comment/aeafc72d_f1beff47 PS1, Line 16: if (fw_config_probe(FW_CONFIG(RPL, IS_RPL))) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174886): https://review.coreboot.org/c/coreboot/+/74727/comment/fe1fc63f_51218d39 PS1, Line 16: if (fw_config_probe(FW_CONFIG(RPL, IS_RPL))) { suspect code indent for conditional statements (8, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174886): https://review.coreboot.org/c/coreboot/+/74727/comment/d40e4f19_cd530942 PS1, Line 19: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174886): https://review.coreboot.org/c/coreboot/+/74727/comment/00a44427_84ffa6aa PS1, Line 19: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174886): https://review.coreboot.org/c/coreboot/+/74727/comment/f713c012_6e33039c PS1, Line 20: else if (fw_config_probe(FW_CONFIG(RPL, NOT_RPL))){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 07:21:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/vat/taeko:Disable C1E for RPL CPU
by Joey Peng (Code Review) 25 Apr '23

25 Apr '23

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: mb/google/brya/vat/taeko:Disable C1E for RPL CPU ...................................................................... mb/google/brya/vat/taeko:Disable C1E for RPL CPU Disable C1E on RPL CPU for improving acoustic noise tests We would use fw_config bit 18 to identify if the CPU is ADL or RPL BUG=b:278654939 TEST:emerge-brya coreboot and check that C1E can be disabled on RPL SKU Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko/variant.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 4 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74727/1 diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index cdfd2ff..67d9a35 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -42,6 +42,9 @@ option HPS_ABSENT 0 option HPS_PRESENT 1 end + field C1E 18 + option C1E_ENABLE 0 + oprion C1E_DISABLE 1 end chip soc/intel/alderlake register "domain_vr_config[VR_DOMAIN_IA]" = "{ diff --git a/src/mainboard/google/brya/variants/taeko/variant.c b/src/mainboard/google/brya/variants/taeko/variant.c index b44e9e3..4b721d7 100644 --- a/src/mainboard/google/brya/variants/taeko/variant.c +++ b/src/mainboard/google/brya/variants/taeko/variant.c @@ -1,9 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <fw_config.h> +#include <baseboard/variants.h> +#include <console/console.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); } + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + // Disable C1E for Tabor + if (fw_config_probe(FW_CONFIG(RPL, IS_RPL))) { + config->c1e = 0; + printk(BIOS_INFO, "Disabling C1E for RPL CPU\n"); + } + else if (fw_config_probe(FW_CONFIG(RPL, NOT_RPL))){ + config->c1e = 1; + printk(BIOS_INFO, "Enabling C1E for ADL CPU\n"); + } +} diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index c466212..969c314 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -681,6 +681,8 @@ * Set this to 1 in order to disable Tccold Handshake */ bool disable_dynamic_tccold_handshake; + + uint8_t c1e; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 7789cec..d0b4876 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1011,6 +1011,8 @@ s_cfg->PkgCStateDemotion = 0; else s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; + + s_cfg->C1e = config->c1e; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: security/tpm: Handle S3 resume logging
by Arthur Heymans (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Tim Crawford, Christian Walter, Julius Werner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74138 ) Change subject: security/tpm: Handle S3 resume logging ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74138/comment/28889636_b3813185 PS1, Line 10: are reset, so the eventlog needs to be reset too. > Uhh... they really shouldn't be. The TPM is supposed to save state (including PCRs) when going into S3 and restore that state on resume. That's what the s3resume argument to tpm_setup() is for. > > If this doesn't work on your board it's probably a problem with that board that needs to be fixed. I know that it works on our Chromebooks, at least. (I'm not entirely sure who sends the TPM2_Shutdown(STATE) command in that case, whether that comes from some SMM handler or the kernel. If it's the kernel maybe there's some extra driver setting you need to enable to get that to work...) I see. Could it be that on S3 resume the SRTM should not measure components on the S3 resume path? Or how should the eventlog / measuring be handled on S3 resume? "This transition is a resume from an S3 suspend state. Host Platform Reset and TPM_INIT are asserted. The SRTM issues the TPM2_Startup(STATE) command, loading the previously saved state, without re-measuring Pre-OS components. The SRTM passes control to the OS. If there are any changes to the Host Platform’s components or configuration, measuring these changes is the responsibility of the OS." -- To view, visit https://review.coreboot.org/c/coreboot/+/74138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7049bf23fea876cdd19103af6e6fd3d5a20ed114 Gerrit-Change-Number: 74138 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Apr 2023 07:17:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Disable Tccold Handshake
by Dtrain Hsu (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74737 to look at the new patch set (#3). Change subject: mb/google/brya/var/omnigul: Disable Tccold Handshake ...................................................................... mb/google/brya/var/omnigul: Disable Tccold Handshake The patch disables Tccold Handshake to prevent possible display flicker issue for Omnigul board. Please refer to Intel doc#723158 for more information. BUG=b: BRANCH=firmware-brya-14505.B TEST=Verify the build for Omnigul board Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/74737/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Gerrit-Change-Number: 74737 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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