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Change subject: mb/google/brya/var/taeko: remove rtd3 for emmc
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Friendly ping.
Since https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… has merged, we would need this CL to be merged as well for eMMC SKUs to boot to OS.
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Change subject: src/mb/facebook/fbg1701/board_mboot.h: Remove config from list
......................................................................
src/mb/facebook/fbg1701/board_mboot.h: Remove config from list
Error message ´Cannot map compressed file config without cbfs_cache' is reported.
Compressed parts of CBFS can not be used during bootblock stage.
Remove config from mb_log_list and add it to verified items.
BUG=NA
TEST=booting and verify log on facebook FBG1701
Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/facebook/fbg1701/board_mboot.h
1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74750/3
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Change subject: mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts
......................................................................
mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts
Update K3KL6L60GM-MGCT support
BRANCH=None
BUG=b:243337816
TEST=emerge-skyrim coreboot
Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59
Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com>
---
M src/mainboard/google/skyrim/variants/winterhold/memory/Makefile.inc
M src/mainboard/google/skyrim/variants/winterhold/memory/dram_id.generated.txt
M src/mainboard/google/skyrim/variants/winterhold/memory/mem_parts_used.txt
3 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74740/4
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Change subject: src/mb/facebook/fbg1701/board_mboot.h: Remove config from list
......................................................................
src/mb/facebook/fbg1701/board_mboot.h: Remove config from list
Error message ´Cannot map compressed file config without cbfs_cache' is reported.
Compressed parts of CBFS can not be used during bootblock stage.
Remove config from mb_log_list and add it to verified items.
BUG=NA
TEST=Boot and verify logging on facebook FBG1701
Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/facebook/fbg1701/board_mboot.h
1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74750/2
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Change subject: mb/google/nissa/var/craask: avoid camera LED blinking during boot
......................................................................
Patch Set 1: Code-Review+1
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Change subject: src/mb/facebook/fbg1701/board_mboot.h: Remove config from list´
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174908):
https://review.coreboot.org/c/coreboot/+/74750/comment/3c112f56_c4587c03
PS1, Line 6:
Possible long commit subject (prefer a maximum 65 characters)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174908):
https://review.coreboot.org/c/coreboot/+/74750/comment/6be09192_fbcfd9c3
PS1, Line 15: TEST=Boot and verify logging on facebook FBG1701
Possible repeated word: 'and'
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74729 )
Change subject: vendorcode/intel/fsp/fsp2_0/alderlake: Remove unused headers
......................................................................
vendorcode/intel/fsp/fsp2_0/alderlake: Remove unused headers
The headers from the FSP repo are used directly.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I58eda4b2f48386c39c9258a4ceacf0d84280397c
---
D src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h
D src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h
D src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
D src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
D src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
5 files changed, 12 insertions(+), 7,576 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74729/1
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Change subject: mb/google/brya/var/taeko:Disable C1E for RPL CPU
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/brya/variants/taeko/variant.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174906):
https://review.coreboot.org/c/coreboot/+/74727/comment/1cda934f_33daac62
PS6, Line 23: else if (cpu_id == CPUID_ALDERLAKE_R0) {
else should follow close brace '}'
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Hello YH Lin, Tarun Tuli, Subrata Banik, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/taeko:Disable C1E for RPL CPU
......................................................................
mb/google/brya/var/taeko:Disable C1E for RPL CPU
Disable C1E on RPL CPU for improving acoustic noise tests
BUG=b:278654939
TEST:emerge-brya coreboot and check that C1E can be disabled on RPL CPU
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342
---
M src/mainboard/google/brya/variants/taeko/variant.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
3 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74727/6
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