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Hello Lance Zhao, build bot (Jenkins), Nico Huber, Tim Wawrzynczak, Maximilian Brune, Werner Zeh, Jan Samek,
I'd like you to reexamine a change. Please visit
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Change subject: acpi: Add a runtime method to override exposed _Sx sleep states
......................................................................
acpi: Add a runtime method to override exposed _Sx sleep states
This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
---
M src/acpi/Kconfig
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/southbridge/intel/common/acpi/sleepstates.asl
4 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74762/6
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Change subject: acpi: Add a runtime method to override exposed _Sx sleep states
......................................................................
Patch Set 5:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/74762/comment/e7f7d39d_fdc03124
PS4, Line 523: assert(!(enable_s1 && CONFIG(PLATFORM_LACKS_ACPI_S1)));
ACPI_S1_NOT_SUPPORTED
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Hello build bot (Jenkins), Paul Menzel, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74761
to look at the new patch set (#5).
Change subject: sb/intel/sleepstates.asl: Use variable to enable sleepstates
......................................................................
sb/intel/sleepstates.asl: Use variable to enable sleepstates
In order to make supported sleep states a runtime configuration option
use a variable. A follow-up patch will implement updating this variable
based on an SSDT generated IntObj.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I6910c2c75e668e6f75a6f431813edeb59d52dd93
---
M src/southbridge/intel/common/acpi/sleepstates.asl
1 file changed, 41 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74761/5
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
soc/intel: Don't report _S1 state when unsupported
Since skylake Intel hardware does not support this sleep state. Trying
to enter S1 by having the OS enter sleep results in a system hang on at
least Alder lake (prodrive/atlas).
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices
support 'skylake style' PMC PCI device for ACPI registers.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
---
M src/Kconfig
M src/soc/intel/common/block/pmc/Kconfig
M src/southbridge/intel/common/acpi/sleepstates.asl
3 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74760/6
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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74760/comment/0d6687c1_fcc0bb30
PS5, Line 10: do enter it
> 1. Remove the *do*? […]
Done
https://review.coreboot.org/c/coreboot/+/74760/comment/e9660e9f_657deddf
PS5, Line 11: Alderlake
> Alder Lake
Done
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/74760/comment/ee67bd18_760de55b
PS5, Line 7: PLATFORM_LACKS_ACPI_S1
> How about ACPI_S1_NOT_SUPPORTED?
I guess my english is lacking :-D
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Change subject: soc/intel/meteorlake: Add config option to choose CSE FW sync in ROMSTAGE
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/74763/comment/0c3d44bc_876b365c
PS1, Line 130:
: if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE))
: cse_fw_sync();
> cse_fw_sync is not required here as you are implementing cse_fw_sync() in ramstage.
this gives the option to mainboard to choose - ROMSTAGE or RAMSTAGE depending on the config flag
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