coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74769 to look at the new patch set (#6). Change subject: soc/intel/meteorlake: Add support of crashlog ...................................................................... soc/intel/meteorlake: Add support of crashlog Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. Bug=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/include/soc/crashlog.h M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 9 files changed, 617 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 6 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by build bot (Jenkins) (Code Review) 26 Apr '23

26 Apr '23

1 0

[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74769 to look at the new patch set (#5). Change subject: soc/intel/meteorlake: Add support of crashlog ...................................................................... soc/intel/meteorlake: Add support of crashlog Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. Bug=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/include/soc/crashlog.h M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 9 files changed, 617 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74769 to look at the new patch set (#4). Change subject: soc/intel/meteorlake: Add support of crashlog ...................................................................... soc/intel/meteorlake: Add support of crashlog Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM are discovered by parsing SOC PMC SRAM records. Bug=b:262501347 TEST=Able to trigger crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/include/soc/crashlog.h M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 9 files changed, 617 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74769 to look at the new patch set (#3). Change subject: soc/intel/meteorlake: Add support of crashlog ...................................................................... soc/intel/meteorlake: Add support of crashlog Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. Bug=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/include/soc/crashlog.h M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 9 files changed, 617 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 3 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by build bot (Jenkins) (Code Review) 26 Apr '23

26 Apr '23

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Enable crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74770 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Enable crashlog ...................................................................... soc/intel/meteorlake: Enable crashlog DO NOT MERGE This patch is added to test crashlog. Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/chipset.cb 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74770/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Gerrit-Change-Number: 74770 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74769 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Add support of crashlog ...................................................................... soc/intel/meteorlake: Add support of crashlog Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. Bug=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/include/soc/crashlog.h M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 9 files changed, 617 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim: Enable SPL fusing on Markarth
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: John Su, Chao Gui, Jason Nien, Martin Roth, Patrick Huang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74753 ) Change subject: mb/google/skyrim: Enable SPL fusing on Markarth ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70 Gerrit-Change-Number: 74753 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Chao Gui <chaogui(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 00:18:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by build bot (Jenkins) (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74769 ) Change subject: soc/intel/meteorlake: Add support of crashlog ...................................................................... Patch Set 1: (51 comments) File src/soc/intel/common/block/crashlog/crashlog.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/e9fee0ec_02e5b078 PS1, Line 23: return 0; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/180c0330_df4821dd PS1, Line 23: return 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/b03424f6_a9104bc9 PS1, Line 78: return false; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/4ce07241_a8eb045a PS1, Line 78: return false; please, no spaces at the start of a line File src/soc/intel/common/block/include/intelblocks/crashlog.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/8913b88d_eae540cf PS1, Line 61: u32 supported :1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/da86f94c_55a3e1b3 PS1, Line 61: u32 supported :1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/7b478262_753370c8 PS1, Line 62: u32 dis :1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/1d25cd17_a56bfc6b PS1, Line 62: u32 dis :1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/e31578c1_20499dd1 PS1, Line 63: u32 discov_mechanism :2; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/f2db3e18_e4f96dac PS1, Line 63: u32 discov_mechanism :2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/eb854c49_73abf6ab PS1, Line 64: u32 size :12; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/fd36015f_81cebbb5 PS1, Line 64: u32 size :12; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/6f94b510_2de40ff0 PS1, Line 65: u32 base_offset :16; /* Start offset of CrashLog in PMC SSRAM */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/77013bf3_caa93fb2 PS1, Line 65: u32 base_offset :16; /* Start offset of CrashLog in PMC SSRAM */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/ed6b90e0_b290a72c PS1, Line 66: u32 rsv :16; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/bb4a6227_6e79cfde PS1, Line 66: u32 rsv :16; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/d8dd0ca2_ffda7161 PS1, Line 67: u32 desc_tabl_offset :16; /* Start offset of descriptor table */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/991db184_4871f7c8 PS1, Line 67: u32 desc_tabl_offset :16; /* Start offset of descriptor table */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/47c729d1_89b2b39a PS1, Line 68: } bits; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/205e51e2_f73a2786 PS1, Line 68: } bits; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/c41aa27e_b6653124 PS1, Line 69: u64 val_64_bits; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/c2c7d3fd_0274e145 PS1, Line 69: u64 val_64_bits; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/9cd15167_a1898462 PS1, Line 76: u32 discov_mechanism :2; /* CrashLog discovery mechanism */ please, no space before tabs File src/soc/intel/meteorlake/crashlog.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/1d0d2040_41aea223 PS1, Line 110: update_new_pmc_crashlog_size(&pmc_crashLog_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/10280aa2_0e67e007 PS1, Line 110: update_new_pmc_crashlog_size(&pmc_crashLog_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/9c5e19bc_76a9dd64 PS1, Line 130: /* process crashlog records for IOE SRAM */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/604573d7_71e2ef4f PS1, Line 195: if ( (discovery_buf.conv_bits64.supported != 1) || (discovery_buf.conv_bits64.discov_mechanism == 0) space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/34d09404_837d0ea5 PS1, Line 210: m_pmc_crashLog_support = true; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/29e49630_42b9c9f8 PS1, Line 210: m_pmc_crashLog_support = true; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/5d501e11_483de69d PS1, Line 213: bar_addr = SPI_BASE_ADDRESS; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/555dd6a8_ea560ec9 PS1, Line 213: bar_addr = SPI_BASE_ADDRESS; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/b552581e_cf31f4e4 PS1, Line 214: pci_write_config32(PCI_DEV_SRAM, PCI_BASE_ADDRESS_0, bar_addr); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/32c37ee2_9d73e937 PS1, Line 214: pci_write_config32(PCI_DEV_SRAM, PCI_BASE_ADDRESS_0, bar_addr); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/edb458d6_7dc650bc PS1, Line 215: pci_or_config16(PCI_DEV_SRAM, PCI_COMMAND, PCI_COMMAND_MEMORY); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/e32c34c5_cdaeabe4 PS1, Line 215: pci_or_config16(PCI_DEV_SRAM, PCI_COMMAND, PCI_COMMAND_MEMORY); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/f269639a_cf16b694 PS1, Line 261: if (pci_read_config16(PCI_DEV_IOE_SRAM, PCI_VENDOR_ID) == 0xFFFF) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/e714c001_a1da3d27 PS1, Line 261: if (pci_read_config16(PCI_DEV_IOE_SRAM, PCI_VENDOR_ID) == 0xFFFF) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/ce497902_69778a73 PS1, Line 262: printk(BIOS_ERR, "IOE SSRAM PCI device disabled. Can be enabled in device tree.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/a0fb731a_7513190a PS1, Line 262: printk(BIOS_ERR, "IOE SSRAM PCI device disabled. Can be enabled in device tree.\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/df6ed57e_c074b789 PS1, Line 263: return false; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/3b07a0ee_e5337307 PS1, Line 263: return false; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/3d3dd2fe_3232b387 PS1, Line 264: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/53242930_75a014f7 PS1, Line 264: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/9b4fd38d_9d2ae610 PS1, Line 265: return true; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/27ea9024_821adf54 PS1, Line 265: return true; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/01433e14_794bfeeb PS1, Line 393: return m_ioe_crashLog_size; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/45235a50_f7c74baa PS1, Line 393: return m_ioe_crashLog_size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/1f6a1f87_468a23c9 PS1, Line 408: return m_ioe_crashLog_present; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/d55a0df8_1c9a4c23 PS1, Line 408: return m_ioe_crashLog_present; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/23e07627_ed2ebd10 PS1, Line 428: m_ioe_crashLog_size = *ioe_crash_size; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174965): https://review.coreboot.org/c/coreboot/+/74769/comment/6950239e_0f4fb1b0 PS1, Line 428: m_ioe_crashLog_size = *ioe_crash_size; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/74769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 00:09:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023