coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: [WIP] soc/intel/meteorlake: Enable crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74770 ) Change subject: [WIP] soc/intel/meteorlake: Enable crashlog ...................................................................... [WIP] soc/intel/meteorlake: Enable crashlog DO NOT MERGE This patch is added to test crashlog. Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/chipset.cb 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74770/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 7762d5f..54bba7c 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -100,6 +100,7 @@ select UDK_202111_BINDING select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI + select SOC_INTEL_CRASHLOG config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT bool diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 57d1205..defd07a 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -83,7 +83,7 @@ device pci 13.0 alias ioe_p2sb hidden end device pci 13.1 alias ieh2 off end device pci 13.2 alias pmc2 hidden end - device pci 13.3 alias shared_sram2 off end + device pci 13.3 alias shared_sram2 on end device pci 14.0 alias xhci off chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" @@ -128,7 +128,7 @@ end end device pci 14.1 alias usb_otg off end - device pci 14.2 alias shared_sram off end + device pci 14.2 alias shared_sram on end device pci 14.3 alias cnvi_wifi off end device pci 14.5 alias ieh off end device pci 15.0 alias i2c0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/74770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Gerrit-Change-Number: 74770 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: soc/intel/meteorlake: Add support of crashlog
by Pratikkumar V Prajapati (Code Review) 26 Apr '23

26 Apr '23

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74769 ) Change subject: soc/intel/meteorlake: Add support of crashlog ...................................................................... soc/intel/meteorlake: Add support of crashlog Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. Bug=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/include/soc/crashlog.h M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 9 files changed, 616 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 4162d84..1d4bced 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -39,6 +39,7 @@ #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_PMC_CRASHLOG 0x504d435f +#define CBMEM_ID_IOE_CRASHLOG 0x504d4360 #define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 diff --git a/src/soc/intel/common/block/acpi/acpi_bert.c b/src/soc/intel/common/block/acpi/acpi_bert.c index 7743ccc..81bacc2 100644 --- a/src/soc/intel/common/block/acpi/acpi_bert.c +++ b/src/soc/intel/common/block/acpi/acpi_bert.c @@ -25,7 +25,7 @@ static enum cb_err record_crashlog_into_bert(void **region, size_t *length) { acpi_generic_error_status_t *status = NULL; - size_t cpu_record_size, pmc_record_size; + size_t cpu_record_size, pmc_record_size, ioe_record_size; size_t gesb_header_size; void *cl_data = NULL; @@ -68,7 +68,7 @@ pmc_record_size = cl_get_pmc_record_size(); if (pmc_record_size) { - /* Allocate new FW ERR structure in case CPU crashlog is present */ + /* Allocate new FW ERR structure in case CPU crashlog is present */ if (cpu_record_size && !bert_append_fw_err(status)) { printk(BIOS_ERR, "Crashlog PMC entry would " "exceed available region\n"); @@ -87,6 +87,27 @@ cl_fill_pmc_records(cl_data); } + ioe_record_size = cl_get_ioe_record_size(); + if (ioe_record_size) { + /* Allocate new FW ERR structure in case IOE crashlog is present */ + if (ioe_record_size && !bert_append_fw_err(status)) { + printk(BIOS_ERR, "Crashlog IOE entry would " + "exceed available region\n"); + return CB_ERR; + } + + cl_data = new_cper_fw_error_crashlog(status, ioe_record_size); + if (!cl_data) { + printk(BIOS_ERR, "Crashlog IOE entry(size %zu) " + "would exceed available region\n", + ioe_record_size); + return CB_ERR; + } + printk(BIOS_DEBUG, "cl_data %p, ioe_record_size %zu\n", + cl_data, ioe_record_size); + cl_fill_ioe_records(cl_data); + } + *length = status->data_length + gesb_header_size; *region = (void *)status; diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index daa5b76..b52847d 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -18,6 +18,11 @@ return 0; } +int __weak cl_get_ioe_record_size(void) +{ + return 0; +} + u32 __weak cl_get_cpu_bar_addr(void) { return 0; @@ -43,6 +48,11 @@ return false; } +bool __weak cl_ioe_sram_has_mmio_access(void) +{ + return false; +} + bool __weak cpu_crashlog_support(void) { return false; @@ -63,10 +73,17 @@ return false; } +bool __weak cl_ioe_data_present(void) +{ + return false; +} + __weak void reset_discovery_buffers(void) {} __weak void update_new_pmc_crashlog_size(u32 *pmc_crash_size) {} +__weak void update_new_ioe_crashlog_size(u32 *ioe_crash_size) {} + __weak void update_new_cpu_crashlog_size(u32 *cpu_crash_size) {} pmc_ipc_discovery_buf_t __weak cl_get_pmc_discovery_buf(void) @@ -271,13 +288,20 @@ u32 src_addr = src_bar + offset; u32 data = read32((u32 *)src_addr); + + /* First 32bits of the record must not be 0xdeadbeef */ + if (data == INVALID_CL) { + printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x\n", + data, offset, src_bar); + return false; + } /* PMC: copy if 1st DWORD in buffer is not zero and its 31st bit is not set */ if (pmc_sram && !(data && !(data & BIT(31)))) { printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x" " of PMC SRAM.\n", data, offset, src_bar); return false; } - /*CPU: don't copy if 1st DWORD in first buffer is zero */ + /* CPU: don't copy if 1st DWORD in first buffer is zero */ if (!pmc_sram && !data && (buffer_index == 0)) { printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x" " of telemetry SRAM.\n", data, offset, src_bar); @@ -295,7 +319,7 @@ return true; } -void cl_get_pmc_sram_data(void) +void __weak cl_get_pmc_sram_data(void) { u32 *dest = NULL; u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); @@ -480,6 +504,10 @@ printk(BIOS_DEBUG, "CPU crash data collection.\n"); cl_src_addr = cbmem_find(CBMEM_ID_CPU_CRASHLOG); + if (!cl_src_addr) { + printk(BIOS_DEBUG, "CPU crash data, CBMEM not found\n"); + return false; + } memcpy(cl_record, cl_src_addr, m_cpu_crashLog_size); return true; @@ -498,7 +526,33 @@ printk(BIOS_DEBUG, "PMC crash data collection.\n"); cl_src_addr = cbmem_find(CBMEM_ID_PMC_CRASHLOG); + if (!cl_src_addr) { + printk(BIOS_DEBUG, "PMC crash data, CBMEM not found\n"); + return false; + } memcpy(cl_record, cl_src_addr, m_pmc_crashLog_size); return true; } + +bool cl_fill_ioe_records(void *cl_record) +{ + void *cl_src_addr = NULL; + + u32 m_ioe_crashLog_size = cl_get_ioe_record_size(); + + if (!cl_ioe_data_present() || m_ioe_crashLog_size == 0) { + printk(BIOS_DEBUG, "IOE crashLog not present, skipping.\n"); + return false; + } + + printk(BIOS_DEBUG, "IOE PMC crash data collection.\n"); + cl_src_addr = cbmem_find(CBMEM_ID_IOE_CRASHLOG); + if (!cl_src_addr) { + printk(BIOS_DEBUG, "IOE crash data, CBMEM not found\n"); + return false; + } + memcpy(cl_record, cl_src_addr, m_ioe_crashLog_size); + + return true; +} diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index 07dd5a2d..5ff783b 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -22,12 +22,18 @@ #define CPU_CRASHLOG_DISC_TAB_GUID_VALID 0x1600 #define CRASHLOG_SIZE_DEBUG_PURPOSE 0x640 +#define INVALID_CL 0xdeadbeef + +/* Tag field definitions */ +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC 0x0 +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE 0x1 /* PMC crashlog discovery structs */ typedef union { struct { - u16 offset; - u16 size; + u16 offset :16; + u16 size :13; + u16 assign_tag :3; } bits; u32 data; } __packed pmc_crashlog_discov_region_t; @@ -45,9 +51,45 @@ u32 size :12; u32 base_offset :16; /* Start offset of CrashLog in PMC SSRAM */ u32 rsv :16; - u32 desc_tabl_offset :16; /* start offset of descriptor table */ + u32 desc_tabl_offset :16; /* Start offset of descriptor table */ } bits; - u64 val_64_bits; + u64 val_64_bits; +} __packed pmc_ipc_discovery_buf_v1_t; + +typedef union { + struct { + u32 supported :1; + u32 dis :1; + u32 discov_mechanism :2; + u32 size :12; + u32 base_offset :16; /* Start offset of CrashLog in PMC SSRAM */ + u32 rsv :16; + u32 desc_tabl_offset :16; /* Start offset of descriptor table */ + } bits; + u64 val_64_bits; + + /* Converged Capability and Status - PMC*/ + struct { + /* Capability */ + u32 supported :1; /* CrashLog feature availability bit */ + u32 dis :1; /* CrashLog Disable bit */ + u32 discov_mechanism :2; /* CrashLog discovery mechanism */ + u32 manu_trig_cmd :1; /* Manuel trigger command */ + u32 clear :1; /* Clear Command */ + u32 all_reset :1; /* Trigger on all reset command */ + u32 re_arm :1; /* Re-arm command */ + u32 glb_rst_trig_mask_sup:1; /* Global reset trigger mask supported */ + u32 rsvd :18; /* Pch Specific reserved */ + /* Status */ + u32 glb_rst_trig_mask_sts :1; /* Global reset trigger mask status */ + u32 crashLog_req :1; /* CrashLog requestor flow */ + u32 trig_armed_sts :1; /* Trigger armed status */ + u32 trig_all_rst :1; /* Trigger on all resets status */ + u32 crash_dis_sts :1; /* Crash log disabled status */ + u32 pch_rsvd :16; /* Pch Specific reserved */ + u32 desc_tabl_offset :16; /* Descriptor Table offset */ + } conv_bits64; + u64 conv_val_64_bits; } __packed pmc_ipc_discovery_buf_t; @@ -115,8 +157,7 @@ typedef union { struct { u32 offset :32; - u32 size :16; - u32 reserved :16; + u32 size :32; } fields; u64 data; } __packed cpu_crashlog_buffer_info_t; @@ -130,19 +171,23 @@ int cl_get_cpu_record_size(void); int cl_get_pmc_record_size(void); +int cl_get_ioe_record_size(void); u32 cl_get_cpu_bar_addr(void); u32 cl_get_cpu_tmp_bar(void); u32 cl_get_cpu_mb_int_addr(void); int cl_get_total_data_size(void); bool cl_pmc_sram_has_mmio_access(void); +bool cl_ioe_sram_has_mmio_access(void); bool cpu_crashlog_support(void); bool pmc_crashlog_support(void); bool cl_cpu_data_present(void); bool cl_pmc_data_present(void); +bool cl_ioe_data_present(void); void cl_get_cpu_sram_data(void); void cl_get_pmc_sram_data(void); void reset_discovery_buffers(void); void update_new_pmc_crashlog_size(u32 *pmc_crash_size); +void update_new_ioe_crashlog_size(u32 *pmc_crash_size); void update_new_cpu_crashlog_size(u32 *cpu_crash_size); pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void); pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void); @@ -168,6 +213,7 @@ void collect_pmc_and_cpu_crashlog_from_srams(void); bool cl_fill_cpu_records(void *cl_record); bool cl_fill_pmc_records(void *cl_record); +bool cl_fill_ioe_records(void *cl_record); static const EFI_GUID FW_ERR_SECTION_GUID = { 0x81212a96, 0x09ed, 0x4996, diff --git a/src/soc/intel/meteorlake/Makefile.inc b/src/soc/intel/meteorlake/Makefile.inc index fd94cda..61e13b8 100644 --- a/src/soc/intel/meteorlake/Makefile.inc +++ b/src/soc/intel/meteorlake/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += tcss.c ramstage-y += xhci.c ramstage-y += soc_info.c +ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c smm-y += elog.c smm-y += gpio.c diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c new file mode 100644 index 0000000..b96ea58 --- /dev/null +++ b/src/soc/intel/meteorlake/crashlog.c @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/bert_storage.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <intelblocks/crashlog.h> +#include <intelblocks/pmc_ipc.h> +#include <soc/crashlog.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <string.h> + +/* global crashLog info */ +static bool m_pmc_crashLog_support; +static bool m_pmc_crashLog_present; +static bool m_cpu_crashLog_support; +static bool m_cpu_crashLog_present; +static bool m_ioe_crashLog_support; +static bool m_ioe_crashLog_present; +static u32 m_pmc_crashLog_size; +static u32 m_ioe_crashLog_size; +static u32 m_cpu_crashLog_size; +static u32 cpu_crash_version; +static pmc_ipc_discovery_buf_t discovery_buf; +static pmc_crashlog_desc_table_t descriptor_table; +static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; +static cpu_crashlog_discovery_table_t cpu_cl_disc_tab; + +u32 __weak cl_get_cpu_mb_int_addr(void) +{ + return CRASHLOG_MAILBOX_INTF_ADDRESS; +} + +void cl_get_pmc_sram_data(void) +{ + u32 *soc_pmc_dest = NULL, *ioe_pmc_dest = NULL; + u32 pmc_sram_base = cl_get_cpu_tmp_bar(); + u32 ioe_sram_base = IOE_PMC_SRAM_ADDRESS; + u32 pmc_crashLog_size = cl_get_pmc_record_size(); + u32 ioe_crashLog_size = 0; + + /* Program BAR 0 and enable command register memory space decoding */ + pci_write_config32(PCI_DEV_IOE_SRAM, PCI_BASE_ADDRESS_0, ioe_sram_base); + pci_or_config16(PCI_DEV_IOE_SRAM, PCI_COMMAND, PCI_COMMAND_MEMORY); + + if (!cl_pmc_sram_has_mmio_access()) + return; + + if (!cl_ioe_sram_has_mmio_access()) + return; + + printk(BIOS_DEBUG, "PMC crashLog size : 0x%x\n", pmc_crashLog_size); + + /* allocate memory for the PMC crash records to be copied */ + unsigned long pmc_cl_cbmem_addr; + + pmc_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_PMC_CRASHLOG, + pmc_crashLog_size); + if (!pmc_cl_cbmem_addr) { + printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n"); + return; + } + + memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size); + soc_pmc_dest = (u32 *)(uintptr_t) pmc_cl_cbmem_addr; + + bool pmc_sram = true; + + /* process crashlog records for SOC PMC SRAM */ + for (int i = 0; i < descriptor_table.numb_regions + 1; i++) { + printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n", + i, + descriptor_table.regions[i].bits.assign_tag, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size); + + if (!descriptor_table.regions[i].bits.size) + continue; + + if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC) { + + if (cl_copy_data_from_sram(pmc_sram_base, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + soc_pmc_dest, + i, + pmc_sram)) { + soc_pmc_dest = (u32 *)((u32)soc_pmc_dest + + (descriptor_table.regions[i].bits.size + * sizeof(u32))); + } else { + pmc_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "PMC crashlog size adjusted to: 0x%x\n", + pmc_crashLog_size); + } + } else if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE) { + /* + * SOC PMC crashlog records contains information about IOE SRAM + * records as well. Calculate IOE records size while parsing SOC + * PME SRAM. + */ + ioe_crashLog_size += descriptor_table.regions[i].bits.size * sizeof(u32); + } + } + + pmc_crashLog_size -= ioe_crashLog_size; + update_new_pmc_crashlog_size(&pmc_crashLog_size); + + if (ioe_crashLog_size) + m_ioe_crashLog_present = true; + else + goto pmc_send_re_arm_after_reset; + + /* allocate memory for the IOE crashlog records to be copied */ + unsigned long ioe_cl_cbmem_addr; + + ioe_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_IOE_CRASHLOG, + ioe_crashLog_size); + if (!ioe_cl_cbmem_addr) { + printk(BIOS_ERR, "Unable to allocate CBMEM IOE crashLog entry.\n"); + return; + } + + memset((void *)ioe_cl_cbmem_addr, 0, ioe_crashLog_size); + ioe_pmc_dest = (u32 *)(uintptr_t) ioe_cl_cbmem_addr; + + /* process crashlog records for IOE SRAM */ + for (int i = 0; i < descriptor_table.numb_regions + 1; i++) { + printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n", + i, + descriptor_table.regions[i].bits.assign_tag, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size); + + if (!descriptor_table.regions[i].bits.size) + continue; + + if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE) { + + if (cl_copy_data_from_sram(ioe_sram_base, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + ioe_pmc_dest, + i, + pmc_sram)) { + ioe_pmc_dest = (u32 *)((u32)ioe_pmc_dest + + (descriptor_table.regions[i].bits.size + * sizeof(u32))); + } else { + + ioe_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "IOE crashlog size adjusted to: 0x%x\n", + ioe_crashLog_size); + } + } + } + + update_new_ioe_crashlog_size(&ioe_crashLog_size); + +pmc_send_re_arm_after_reset: + /* when bit 7 of discov cmd resp is set -> bit 2 of size field */ + cl_pmc_re_arm_after_reset(); + + /* Clear the SSRAM region after copying the error log */ + cl_pmc_clear(); +} + +bool pmc_cl_discovery(void) +{ + u32 bar_addr = 0, desc_table_addr = 0; + + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; + uint32_t cmd_reg; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY, + PMC_IPC_CMD_SIZE_SHIFT); + printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d in %s\n", cmd_reg, __func__); + + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); + return false; + } + discovery_buf.conv_val_64_bits = ((u64)res.buf[1] << 32) | res.buf[0]; + + if ( (discovery_buf.conv_bits64.supported != 1) || (discovery_buf.conv_bits64.discov_mechanism == 0) + || (discovery_buf.conv_bits64.crash_dis_sts == 1)) { + printk(BIOS_INFO, "PCH crashlog feature not supported.\n"); + m_pmc_crashLog_support = false; + m_ioe_crashLog_support = false; + m_pmc_crashLog_size = 0; + m_ioe_crashLog_size = 0; + printk(BIOS_DEBUG, "discovery_buf supported: %d, mechanism: %d, CrashDisSts: %d\n", + discovery_buf.conv_bits64.supported, + discovery_buf.conv_bits64.discov_mechanism, + discovery_buf.conv_bits64.crash_dis_sts); + return false; + } + + printk(BIOS_INFO, "PMC crashlog feature is supported.\n"); + m_pmc_crashLog_support = true; + + /* Program BAR 0 and enable command register memory space decoding */ + bar_addr = SPI_BASE_ADDRESS; + pci_write_config32(PCI_DEV_SRAM, PCI_BASE_ADDRESS_0, bar_addr); + pci_or_config16(PCI_DEV_SRAM, PCI_COMMAND, PCI_COMMAND_MEMORY); + + desc_table_addr = bar_addr + discovery_buf.conv_bits64.desc_tabl_offset; + m_pmc_crashLog_size = pmc_cl_gen_descriptor_table(desc_table_addr, + &descriptor_table); + printk(BIOS_DEBUG, "PMC CrashLog size in discovery mode: 0x%X\n", + m_pmc_crashLog_size); + m_pmc_crashLog_present = m_pmc_crashLog_size > 0; + + return true; +} + +u32 cl_get_cpu_bar_addr(void) +{ + u32 base_addr = 0; + if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { + base_addr = pci_read_config32(PCI_DEV_TMT, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { + base_addr = pci_read_config32(PCI_DEV_TMT, PCI_BASE_ADDRESS_1) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } else { + printk(BIOS_ERR, "Invalid TEL_CFG_BAR value %d, discovery failure expected.\n", + cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); + } + + return base_addr; +} + +u32 cl_get_cpu_tmp_bar(void) +{ + return SPI_BASE_ADDRESS; +} + +bool cl_pmc_sram_has_mmio_access(void) +{ + if (pci_read_config16(PCI_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_ERR, "PMC SSRAM PCI device disabled. Can be enabled in device tree.\n"); + return false; + } + + return true; +} + +bool cl_ioe_sram_has_mmio_access(void) +{ + if (pci_read_config16(PCI_DEV_IOE_SRAM, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_ERR, "IOE SSRAM PCI device disabled. Can be enabled in device tree.\n"); + return false; + } + return true; +} + +static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap) +{ + cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TMT, + TEL_DVSEC_OFFSET + TEL_DVSEC_PCIE_CAP_ID); + if (cl_devsc_cap->cap_data.fields.pcie_cap_id != TELEMETRY_EXTENDED_CAP_ID) { + printk(BIOS_DEBUG, "Read ID for Telemetry: 0x%x differs from expected: 0x%x\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id, TELEMETRY_EXTENDED_CAP_ID); + return false; + } + + /* walk through the entries until crashLog entry */ + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TMT, TEL_DVSEV_ID); + int new_offset = 0; + while (cl_devsc_cap->devsc_data.fields.devsc_id != CRASHLOG_DVSEC_ID) { + if (cl_devsc_cap->cap_data.fields.next_cap_offset == 0 + || cl_devsc_cap->cap_data.fields.next_cap_offset == 0xFFFF) { + printk(BIOS_DEBUG, "Read invalid pcie_cap_id value: 0x%x\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id); + return false; + } + new_offset = cl_devsc_cap->cap_data.fields.next_cap_offset; + cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TMT, + new_offset + TEL_DVSEC_PCIE_CAP_ID); + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TMT, + new_offset + TEL_DVSEV_ID); + } + cpu_crash_version = cl_devsc_cap->devsc_data.fields.devsc_ver; + + cl_devsc_cap->discovery_data.data = pci_read_config32(PCI_DEV_TMT, new_offset + + TEL_DVSEV_DISCOVERY_TABLE_OFFSET); + + return true; +} + +static bool cpu_cl_gen_discovery_table(void) +{ + u32 bar_addr = 0, disc_tab_addr = 0; + bar_addr = cl_get_cpu_bar_addr(); + disc_tab_addr = bar_addr + + cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset; + memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t)); + + printk(BIOS_DEBUG, "cpu discovery table offset: 0x%x\n", + cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset); + + cpu_cl_disc_tab.header.data = ((u64)read32((u32 *)disc_tab_addr) + + ((u64)read32((u32 *)(disc_tab_addr + 4)) << 32)); + + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n", + cpu_cl_disc_tab.header.fields.count); + + int cur_offset = 0; + for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { + cur_offset = 8 + 24*i; + cpu_cl_disc_tab.buffers[i].data = ((u64)read32((u32 *)(disc_tab_addr + + cur_offset)) + ((u64)read32((u32 *) + (disc_tab_addr + cur_offset + 4)) << 32)); + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " + "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, + cpu_cl_disc_tab.buffers[i].fields.offset); + m_cpu_crashLog_size += cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32); + } + + m_cpu_crashLog_present = m_cpu_crashLog_size > 0; + + return true; +} + +bool cpu_cl_discovery(void) +{ + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); + + if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) { + printk(BIOS_ERR, "CPU crashlog capability not found.\n"); + m_cpu_crashLog_support = false; + return false; + } + + m_cpu_crashLog_support = true; + + if (!cpu_cl_gen_discovery_table()) { + printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n"); + m_cpu_crashLog_present = false; + return false; + } + + return true; +} + +void reset_discovery_buffers(void) +{ + memset(&discovery_buf, 0, sizeof(pmc_ipc_discovery_buf_t)); + memset(&descriptor_table, 0, sizeof(pmc_crashlog_desc_table_t)); + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); +} + +int cl_get_total_data_size(void) +{ + printk(BIOS_DEBUG, "crashlog size:pmc-0x%x, ioe-pmc-0x%x cpu-0x%x\n", + m_pmc_crashLog_size, m_ioe_crashLog_size, m_cpu_crashLog_size); + return m_pmc_crashLog_size + m_cpu_crashLog_size + m_ioe_crashLog_size; +} + +pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void) +{ + return discovery_buf; +} + +pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void) +{ + return descriptor_table; +} + +int cl_get_pmc_record_size(void) +{ + return m_pmc_crashLog_size; +} + +int cl_get_cpu_record_size(void) +{ + return m_cpu_crashLog_size; +} + +int cl_get_ioe_record_size(void) +{ + return m_ioe_crashLog_size; +} + +bool cl_cpu_data_present(void) +{ + return m_cpu_crashLog_present; +} + +bool cl_pmc_data_present(void) +{ + return m_pmc_crashLog_present; +} + +bool cl_ioe_data_present(void) +{ + return m_ioe_crashLog_present; +} + +bool cpu_crashlog_support(void) +{ + return m_cpu_crashLog_support; +} + +bool pmc_crashlog_support(void) +{ + return m_pmc_crashLog_support; +} + +void update_new_pmc_crashlog_size(u32 *pmc_crash_size) +{ + m_pmc_crashLog_size = *pmc_crash_size; +} + +void update_new_ioe_crashlog_size(u32 *ioe_crash_size) +{ + m_ioe_crashLog_size = *ioe_crash_size; +} + +cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void) +{ + return cpu_cl_disc_tab; +} + +void update_new_cpu_crashlog_size(u32 *cpu_crash_size) +{ + m_cpu_crashLog_size = *cpu_crash_size; +} diff --git a/src/soc/intel/meteorlake/include/soc/crashlog.h b/src/soc/intel/meteorlake/include/soc/crashlog.h new file mode 100644 index 0000000..4435d48 --- /dev/null +++ b/src/soc/intel/meteorlake/include/soc/crashlog.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_COMMON_BLOCK_CRASHLOG_LIB_H_ +#define _SOC_COMMON_BLOCK_CRASHLIB_LIB_H_ + +#include <types.h> + +/* DVSEC capability Registers */ +#define TEL_DVSEC_OFFSET 0x100 +#define TEL_DVSEC_PCIE_CAP_ID 0x0 +#define TEL_DVSEV_ID 0x8 +#define TEL_DVSEV_DISCOVERY_TABLE_OFFSET 0xC +#define TELEMETRY_EXTENDED_CAP_ID 0x23 +#define CRASHLOG_DVSEC_ID 0x04 +#define TEL_DVSEC_TBIR_BAR0 0 +#define TEL_DVSEC_TBIR_BAR1 1 + +/* CPU CrashLog MMIO Registers */ +#define CRASHLOG_MAILBOX_INTF_ADDRESS 0x6038 + +#endif /* _SOC_COMMON_BLOCK_CRASHLOG_LIB_H_ */ diff --git a/src/soc/intel/meteorlake/include/soc/iomap.h b/src/soc/intel/meteorlake/include/soc/iomap.h index a2df40c..31fb753 100644 --- a/src/soc/intel/meteorlake/include/soc/iomap.h +++ b/src/soc/intel/meteorlake/include/soc/iomap.h @@ -54,6 +54,7 @@ #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) #define SPI_BASE_ADDRESS 0xfe010000 +#define IOE_PMC_SRAM_ADDRESS 0xfe420000 #define REG_BASE_ADDRESS 0xd0000000 #define REG_BASE_SIZE (256 * MiB) diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index 1c4e9b2..43f4d6a 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -60,6 +60,10 @@ #define PCI_DEVFN_GNA _PCI_DEVFN(GNA, 0) #define PCI_DEV_GNA _PCI_DEV(GNA, 0) +#define PCI_DEV_SLOT_TMT 0x0A +#define PCI_DEVFN_TMT _PCI_DEVFN(TMT, 0) +#define PCI_DEV_TMT _PCI_DEV(TMT, 0) + #define PCI_DEV_SLOT_TCSS 0x0d #define NUM_TCSS_DMA_FUNCTIONS 2 #define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) -- To view, visit https://review.coreboot.org/c/coreboot/+/74769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/myst: Inject SPD binaries to APCB
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74746 ) Change subject: mb/google/myst: Inject SPD binaries to APCB ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Gerrit-Change-Number: 74746 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 00:01:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Add initial memory configuration
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74745 ) Change subject: mb/google/myst: Add initial memory configuration ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612 Gerrit-Change-Number: 74745 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 23:59:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Inject SPD binaries to APCB
by Karthik Ramasubramanian (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Jon Murphy, Eric Lai, Martin Roth, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74746 ) Change subject: mb/google/myst: Inject SPD binaries to APCB ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/myst/Makefile.inc: https://review.coreboot.org/c/coreboot/+/74746/comment/fd1d32fa_e9361b3b PS1, Line 18: APCB_PHX_D5 > It might be too early to answer, but any thoughts on how we'll handle multiple SOC generations/refre […] Is this question specific to APCB? In theory, APCB is binary compatible across SOC refreshes. We have to see how it rolls out in practice. Regarding SoC generations, APCB is definitely different between MDN and PHX if that is what you meant as generation. So it will not be compatible. -- To view, visit https://review.coreboot.org/c/coreboot/+/74746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Gerrit-Change-Number: 74746 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 23:42:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Inject SPD binaries to APCB
by Tim Van Patten (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Jon Murphy, Eric Lai, Martin Roth, Karthik Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74746 ) Change subject: mb/google/myst: Inject SPD binaries to APCB ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/google/myst/Makefile.inc: https://review.coreboot.org/c/coreboot/+/74746/comment/695ca293_345b8350 PS1, Line 18: APCB_PHX_D5 It might be too early to answer, but any thoughts on how we'll handle multiple SOC generations/refreshes? Will we drop support for older SOCs and just move entirely to the new one? -- To view, visit https://review.coreboot.org/c/coreboot/+/74746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Gerrit-Change-Number: 74746 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 23:17:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Inject SPD binaries to APCB
by Karthik Ramasubramanian (Code Review) 26 Apr '23

26 Apr '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74746 ) Change subject: mb/google/myst: Inject SPD binaries to APCB ...................................................................... mb/google/myst: Inject SPD binaries to APCB Add rules to inject the variant specific SPD binaries into APCB. BUG=b:273383819 TEST=Build Myst BIOS image. Currently no APCB is present. So no SPD is injected into APCB. Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/myst/Makefile.inc 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/74746/1 diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc index 418ff9e..136966e 100644 --- a/src/mainboard/google/myst/Makefile.inc +++ b/src/mainboard/google/myst/Makefile.inc @@ -14,3 +14,30 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +APCB_NAME=APCB_PHX_D5 + +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin),) +$(info APCB sources present.) + +ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/Makefile.inc),) + +LIB_SPD_DEPS = $(SPD_SOURCES) + +APCB_SOURCES = $(obj)/$(APCB_NAME).gen + +$(obj)/$(APCB_NAME).gen: $(SPD_SOURCES) \ + $(APCB_V3_EDIT_TOOL) \ + $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin + $(APCB_V3_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/$(APCB_NAME).bin \ + $(obj)/$(APCB_NAME).gen \ + --spd_sources $(SPD_SOURCES) \ + --mem_type 'lp5' +else +$(info SPD sources not found. Skipping APCB.) +files_added:: die_no_apcb +endif +else +$(info APCB sources not found. Skipping APCB.) +files_added:: warn_no_apcb +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Gerrit-Change-Number: 74746 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/myst: Add initial memory configuration
by Karthik Ramasubramanian (Code Review) 26 Apr '23

26 Apr '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74745 ) Change subject: mb/google/myst: Add initial memory configuration ...................................................................... mb/google/myst: Add initial memory configuration Generate the RAM Strap IDs based on the initial memory configuration. BUG=b:272746814 TEST=Build Myst BIOS image. Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- A src/mainboard/google/myst/variants/myst/memory/Makefile.inc A src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt A src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/74745/1 diff --git a/src/mainboard/google/myst/variants/myst/memory/Makefile.inc b/src/mainboard/google/myst/variants/myst/memory/Makefile.inc new file mode 100644 index 0000000..70188b4 --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/memory/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen PHX lp5 src/mainboard/google/myst/variants/myst/memory src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-1/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt b/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt new file mode 100644 index 0000000..8276871 --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen PHX lp5 src/mainboard/google/myst/variants/myst/memory src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +H9JCNNNCP3MLYR-N6E 0 (0000) diff --git a/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt b/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt new file mode 100644 index 0000000..283740b --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt @@ -0,0 +1,2 @@ +MT62F1G32D4DR-031 WT:B, +H9JCNNNCP3MLYR-N6E, -- To view, visit https://review.coreboot.org/c/coreboot/+/74745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612 Gerrit-Change-Number: 74745 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: RFC: util/sconfig: Add include keyword
by Karthik Ramasubramanian (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: RFC: util/sconfig: Add include keyword ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74736/comment/33d8aab8_27054469 PS1, Line 9: Include > The mainboard device tree is passed in via `-m`, so we could either: […] I thought about adding an option to update the name of the mainboard chip. But your suggestion is even less intrusive. I can do that if there is general consensus. -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Apr 2023 22:16:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: RFC: util/sconfig: Add include keyword
by Raul Rangel (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: RFC: util/sconfig: Add include keyword ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74736/comment/b997c446_c8046a3b PS1, Line 9: Include > > Honestly though we already define a "mainboard" chip, […] The mainboard device tree is passed in via `-m`, so we could either: `stat(dirname(m) + "/chip.h")`, or update the mainboard_chip.name with the name derived from `m`. I think the former is easier IMO. -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Apr 2023 21:45:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023