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Change subject: soc/amd/common/block/graphics: Add missing cbfs_unmap()
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74779/comment/de9a329a_f7580967
PS1, Line 9: cbfs_map() can allocate memory, so cbfs_unmap() should be
: called before leaving the function.
This needs to be updated, since `cbfs_unmap()` isn't being called here anymore.
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Change subject: vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule
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Patch Set 2: Code-Review+2
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Change subject: soc/amd/common/block/graphics: Add missing cbfs_unmap()
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Change subject: src/mainboard/rex: Perform CSE FW update in RAMSTAGE
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rex/Kconfig:
https://review.coreboot.org/c/coreboot/+/74764/comment/9436d9f6_337af2ff
PS1, Line 45: select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
> there is a dependency being set in Kconfig
> config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
> Â Â Â Â Â Â Â bool
> Â Â Â Â Â Â Â default n
> Â Â Â Â Â Â Â depends on SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
> Â Â Â Â Â Â Â help
> Â Â Â Â Â Â Â Â Use this option for CSE FW Update when compressed blobs are used.
can u please try to decouple this logic. doesn't make any sense
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Change subject: src/mainboard/rex: Perform CSE FW update in RAMSTAGE
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rex/Kconfig:
https://review.coreboot.org/c/coreboot/+/74764/comment/800de8c0_dae39d21
PS1, Line 45: select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
> exactly that was my understanding too. […]
there is a dependency being set in Kconfig
config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
       bool
       default n
       depends on SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
       help
        Use this option for CSE FW Update when compressed blobs are used.
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Change subject: vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74788/comment/5470b4a1_e2cf94fb
PS1, Line 7: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP
> maybe: vc/amd/fsp/mendocino: Add UPD to set eDP T9 value
Done
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Hello Jason Glenesk, build bot (Jenkins), Jason Nien, Matt DeVillier, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
......................................................................
mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
Set edp_panel_t9_ms to 8ms which means it will delay 8ms
between backlight off and vary backlight off.
BUG=b:271704149
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table;
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268
---
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/74790/3
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule
......................................................................
vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule
Add UPD edp_panel_t9_ms for eDP panel sequence adjustment.
BUG=b:271704149
BRANCH=none
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
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---
M src/vendorcode/amd/fsp/mendocino/FspmUpd.h
1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74788/2
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Hello Jason Glenesk, build bot (Jenkins), Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment
......................................................................
soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment
Add UPD parameter for eDP power sequence adjustment.
The edp_panel_t9_ms parameter is set for bloff to varybloff.
BUG=b:271704149
TEST=Build; Verify the UPD was pass to system integrated table.
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b
---
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fsp_m_params.c
2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/74789/2
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