Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74797 )
Change subject: cpu/x86/reset16.S: Remove handcoded reset vector
......................................................................
cpu/x86/reset16.S: Remove handcoded reset vector
Only 3 bytes should be used for the reset vector and it looks like
modern tooling has no problem with using a regular relative jump
instruction.
TESTED: Qemu Q35 still boots fine.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ie371000c60d66c032a8dcccb98e7627df09d3aa4
---
M src/cpu/x86/reset16.S
1 file changed, 17 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/74797/1
diff --git a/src/cpu/x86/reset16.S b/src/cpu/x86/reset16.S
index 3858014..9cc85c9 100644
--- a/src/cpu/x86/reset16.S
+++ b/src/cpu/x86/reset16.S
@@ -4,11 +4,4 @@
.code16
.globl _start
_start:
- .byte 0xe9
- .int _start16bit - ( . + 2 )
- /* Note: The above jump is hand coded to work around bugs in binutils.
- * 5 byte are used for a 3 byte instruction. This works because x86
- * is little endian and allows us to use supported 32bit relocations
- * instead of the weird 16 bit relocations that binutils does not
- * handle consistently between versions because they are used so rarely.
- */
+ jmp _start16bit
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74357
to look at the new patch set (#3).
Change subject: soc/amd: Drop acpi_fill_madt_irqoverride()
......................................................................
soc/amd: Drop acpi_fill_madt_irqoverride()
It is unused. The use of field irq is problematic as it should
appear relative to IOAPIC GSI bases in the devicetree.
Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/cezanne/acpi.c
M src/soc/amd/common/block/acpi/tables.c
M src/soc/amd/common/block/include/amdblocks/acpi.h
M src/soc/amd/common/block/include/amdblocks/chip.h
M src/soc/amd/glinda/acpi.c
M src/soc/amd/mendocino/acpi.c
M src/soc/amd/phoenix/acpi.c
M src/soc/amd/picasso/acpi.c
8 files changed, 13 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74357/3
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74357 )
Change subject: soc/amd: Drop acpi_fill_madt_irqoverride()
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
when dropping this, please also drop the corresponding irq_override array in soc/amd/common/block/include/amdblocks/chip.h, to not have that as a leftover.
verified that this is unused in upstream and if it turns out that it will be needed, it can be brought back again
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74600 )
Change subject: ACPI: Make FADT entries for SMI architectural
......................................................................
Patch Set 2: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74715 )
Change subject: acpi: Add missing cbfs_unmap()
......................................................................
Patch Set 3:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/74715/comment/0509364d_db677699
PS2, Line 1934: cbfs_unmap(dsdt_file);
> > As long as you don't overflow your heap, there aren't any problems with this approach. […]
Your point about better documentation is incredibly valid ;) There are patches that come up randomly sometimes that are trying to "fix" mallocs() that don't free(), it would be better to have some authoritative place to point to saying this is our current strategy.
Maybe `free()` should be renamed to `maybe_free()` or `free_latest()` just as examples to help avoid this confusion.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74783 )
Change subject: soc/intel/common: Introduce API to get the FSP Reset Status
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74783/comment/30809dc4_0381904c
PS2, Line 14: Ideally FSP API should be able to return the status (both success and
: error code) upon exiting the FSP API but unfortunately there are some
: scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return
: any ERROR status. Hence, this function provides an additional hook to
: read the FSP reset status by reading the dedicated HOB without relying
: on the FSP API exit status code.
Is that dependent on the FSP version, that means, will it be fixed in a future version?
Can this FSP bug detected at runtime?
File src/soc/intel/common/fsp_reset.c:
https://review.coreboot.org/c/coreboot/+/74783/comment/5aae56f8_b191e909
PS2, Line 56: size_t size = 0;
You do not seem to use `size`, so there is no need if it’s uninitialized.
File src/soc/intel/common/reset.h:
https://review.coreboot.org/c/coreboot/+/74783/comment/b56eb6d0_f123a590
PS2, Line 22: th
the
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Change subject: arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] define
......................................................................
Patch Set 2: Code-Review+2
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