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Hello build bot (Jenkins), Werner Zeh, Jan Samek,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/siemens/mc_ehl*: Correct comment in gpio.c
......................................................................
mb/siemens/mc_ehl*: Correct comment in gpio.c
There were two wrong comments in all mc_ehl gpio.c files. This patch
corrects the incorrect comments.
Change-Id: Iea356db177227d89b91be32a4e2367c612b77350
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c
3 files changed, 19 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/72458/4
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/siemens/mc_ehl4: Remove TPM from devicetree and Kconfig
......................................................................
mb/siemens/mc_ehl4: Remove TPM from devicetree and Kconfig
This mainboard does not use security features like TPM.
Change-Id: Ieebbf12fc844573ffadb089da78062dd2033517a
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
2 files changed, 13 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/72429/4
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Hello Werner Zeh,
I'd like you to reexamine a change. Please visit
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Change subject: mb/siemens/mc_ehl: Move TPM Kconfig switches to variants
......................................................................
mb/siemens/mc_ehl: Move TPM Kconfig switches to variants
The upcoming mc_ehl4 variant is the first Siemens Elkhart Lake mainboard
without a TPM. For this reason, the corresponding Kconfig switches must
be moved to variant level. To prevent Jenkins build from complaining,
the TPM is removed in the following patch.
Change-Id: Ic73ccd1b52e57c1cf1dd7337b0e28beaadbece8e
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/Kconfig
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Kconfig
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
5 files changed, 31 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/72428/4
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Gerrit-Change-Number: 72428
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72804 )
Change subject: mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s
......................................................................
mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s
The currently used panel type could work with 500 ms but increasing
the value to 1 second allows to use a wider range of LVDS LCD panels,
as many of them specify the delay of 1 s as minimum.
BUG=none
TEST=Test link stability using a panel with minimum re-power delay of
1 s.
Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b
Signed-off-by: Jan Samek <jan.samek(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72804
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
1 file changed, 23 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
index 316eb71..965f62d 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
@@ -82,8 +82,8 @@
cfg->t2_delay = 0x01;
/* LVDS to backlight active delay: 200 ms */
cfg->t3_timing = 0x04;
- /* Minimum re-power delay: 500 ms */
- cfg->t12_timing = 0x0a;
+ /* Minimum re-power delay: 1 s */
+ cfg->t12_timing = 0x14;
/* Backlight off to LVDS inactive delay: 200 ms */
cfg->t4_timing = 0x04;
/* Enable LVDS to VDD inactive delay. */
--
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Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71715 )
Change subject: soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
......................................................................
soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this GPIO to 1 or 0 will not change the HDA
GPIO configuration; it will make the sound work when set to 1,
or not work when set to 0.
Remove the incorrect comment and make the UPD configurable from the
devicetree.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 26 insertions(+), 7 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, but someone else must approve
Michał Żygowski: Looks good to me, approved
Lean Sheng Tan: Looks good to me, approved
Eric Lai: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index cea63bf..04a4a22 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -348,6 +348,7 @@
uint16_t sata_ports_dito_val[8];
/* Audio related */
+ uint8_t pch_hda_audio_link_hda_enable;
uint8_t pch_hda_dsp_enable;
/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 6016bff..f18e1f4 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -242,13 +242,7 @@
m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
- /*
- * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
- * configure GPIO pads for audio. Mainboard is expected to perform all GPIO
- * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
- * configuration for audio pads.
- */
- m_cfg->PchHdaAudioLinkHdaEnable = 0;
+ m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;
memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
--
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73018 )
Change subject: drivers/net/phy/m88e1512: Add a way to set output impedance manually
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/siemens/mc_ehl4: Remove TPM from devicetree
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/brya/acpi: Remove extra DC boost byte
......................................................................
Patch Set 3: Code-Review+2
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Change subject: amdfwtool: Move the filling of table headers into functions
......................................................................
Patch Set 9: Code-Review+2
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