coreboot-gerrit March 2023

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[S] Change in coreboot[master]: soc/amd/mendocino: Add STT support for dptc tablet mode
by Tim Van Patten (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Isaac Lee, Chris Wang, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73205 ) Change subject: soc/amd/mendocino: Add STT support for dptc tablet mode ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4aad3af8761b20084717b15a462edf4704b83cc Gerrit-Change-Number: 73205 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 23:45:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter
by Tim Van Patten (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Chris Wang, Martin Roth, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73124 ) Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > The sustained_power_limit_mW_x will be removed from chip.h and overridetree also in each variant. […] Why is `sustained_power_limit_mW` staying when using it is an error? What prevents someone from changing it in the device tree in the future? -- To view, visit https://review.coreboot.org/c/coreboot/+/73124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Gerrit-Change-Number: 73124 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 23:43:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/brya: remove the skolas baseboard
by Tarun Tuli (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73388 ) Change subject: mb/google/brya: remove the skolas baseboard ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Gerrit-Change-Number: 73388 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 23:24:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Disable USE_SELECTIVE_GOP_INIT
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73393 ) Change subject: mb/google/skyrim: Disable USE_SELECTIVE_GOP_INIT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Gerrit-Change-Number: 73393 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 21:53:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/brya: remove the skolas baseboard
by Nick Vaccaro (Code Review) 02 Mar '23

02 Mar '23

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73388 ) Change subject: mb/google/brya: remove the skolas baseboard ...................................................................... mb/google/brya: remove the skolas baseboard The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name D src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc D src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb D src/mainboard/google/brya/variants/baseboard/skolas/gpio.c D src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h D src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h D src/mainboard/google/brya/variants/baseboard/skolas/memory.c D src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c 9 files changed, 25 insertions(+), 898 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/73388/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b3e804c..b0bdfc4 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -89,18 +89,6 @@ select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE -config BOARD_GOOGLE_BASEBOARD_SKOLAS - def_bool n - select BOARD_GOOGLE_BRYA_COMMON - select BOARD_ROMSIZE_KB_32768 - select HAVE_SLP_S0_GATE - select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE - select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - select SOC_INTEL_RAPTORLAKE - select SYSTEM_TYPE_LAPTOP - select TPM_GOOGLE_CR50 - if BOARD_GOOGLE_BRYA_COMMON config BASEBOARD_DIR @@ -109,7 +97,6 @@ default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK default "hades" if BOARD_GOOGLE_BASEBOARD_HADES default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA - default "skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES @@ -199,7 +186,6 @@ default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK default "Google_Hades" if BOARD_GOOGLE_BASEBOARD_HADES default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA - default "Google_Skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS config MAINBOARD_PART_NUMBER default "Brya" if BOARD_GOOGLE_BRYA0 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 71b36ac..f63efdf 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -142,7 +142,8 @@ config BOARD_GOOGLE_SKOLAS bool "-> Skolas" - select BOARD_GOOGLE_BASEBOARD_SKOLAS + select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_SX9324 @@ -151,7 +152,8 @@ config BOARD_GOOGLE_SKOLAS4ES bool "-> Skolas4ES" - select BOARD_GOOGLE_BASEBOARD_SKOLAS + select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DEFAULT_ADL_NEM select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA @@ -303,7 +305,8 @@ config BOARD_GOOGLE_ZYDRON bool "-> Zydron" - select BOARD_GOOGLE_BASEBOARD_SKOLAS + select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DEFAULT_ADL_NEM select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_NAU8825 diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc deleted file mode 100644 index 8a4b2ac..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -bootblock-y += gpio.c - -romstage-y += memory.c -romstage-y += gpio.c - -ramstage-y += gpio.c -ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb deleted file mode 100644 index 70e7779..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb +++ /dev/null @@ -1,171 +0,0 @@ -chip soc/intel/alderlake - - # GPE configuration - register "pmc_gpe0_dw0" = "GPP_A" - register "pmc_gpe0_dw1" = "GPP_E" - register "pmc_gpe0_dw2" = "GPP_F" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - # S0ix enable - register "s0ix_enable" = "1" - - # DPTF enable - register "dptf_enable" = "1" - - register "tcc_offset" = "10" # TCC of 90 - - # Enable CNVi BT - register "cnvi_bt_core" = "true" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - - register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" - register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" - register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" - - register "serial_io_i2c_mode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "serial_io_gspi_mode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - }" - - register "serial_io_uart_mode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoPci, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" - register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" - register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" - register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" - register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" - - # HD Audio - register "pch_hda_dsp_enable" = "1" - register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" - register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" - register "pch_hda_idisp_codec_enable" = "1" - - # FIVR RFI Spread Spectrum 1.5% - register "fivr_spread_spectrum" = "FIVR_SS_1_5" - - # Disable C state auto-demotion for all brya baseboards - register "disable_c1_state_auto_demotion" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio and WFC | - #| I2C1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| I2C2 | SAR0 | - #| I2C3 | Touchscreen | - #| I2C5 | Trackpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 900, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[3] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 600, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - }" - - device domain 0 on - device ref igpu on end - device ref dtt on end - device ref tbt_pcie_rp0 on end - device ref tbt_pcie_rp1 on end - device ref tbt_pcie_rp2 on end - device ref tcss_xhci on end - device ref tcss_dma0 on end - device ref tcss_dma1 on end - device ref xhci on end - device ref shared_sram on end - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - register "add_acpi_dma_property" = "true" - device generic 0 on end - end - end - device ref i2c3 on end - device ref heci1 on end - device ref sata on end - device ref pcie_rp8 on - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card - device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 1 - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE9-12 SSD - device ref uart0 on end - device ref gspi1 on end - device ref pch_espi on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref hda on end - end -end diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c b/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c deleted file mode 100644 index cd0be69..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <types.h> -#include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { - /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */ - /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ - /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ - /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ - /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ - /* A4 : ESPI_CS# ==> ESPI_CS_L */ - /* A5 : ESPI_ALERT0# ==> NC */ - PAD_NC(GPP_A5, NONE), - /* A6 : ESPI_ALERT1# ==> SPKR_INT_L */ - PAD_CFG_GPI(GPP_A6, NONE, DEEP), - /* A7 : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT), - /* A8 : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */ - PAD_CFG_GPO(GPP_A8, 1, DEEP), - /* A9 : ESPI_CLK ==> ESPI_CLK */ - /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ - /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ - PAD_CFG_GPO(GPP_A11, 1, DEEP), - /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ - PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG), - /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_A17, 1, DEEP), - /* A18 : DDSP_HPDB ==> HDMI_HPD */ - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6), - /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6), - /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */ - PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), - /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */ - PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), - /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ - PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), - - /* B0 : SOC_VID0 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - /* B1 : SOC_VID1 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> M2_SSD_PLA_L */ - PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG), - /* B3 : PROC_GP2 ==> SAR2_INT_L */ - PAD_CFG_GPI_APIC_LOCK(GPP_B3, NONE, LEVEL, NONE, LOCK_CONFIG), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), - /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ - PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), - /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ - PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), - /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), - /* B9 : NC */ - PAD_NC(GPP_B9, NONE), - /* B10 : NC */ - PAD_NC(GPP_B10, NONE), - /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_B11, 1, DEEP), - /* B12 : SLP_S0# ==> SLP_S0_L */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* B13 : PLTRST# ==> PLT_RST_L */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* B14 : SPKR ==> GPP_B14_STRAP */ - PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG), - /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */ - PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG), - /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ - PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), - /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ - PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), - /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ - PAD_NC(GPP_B18, NONE), - /* B19 : NC */ - PAD_NC(GPP_B19, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ - PAD_NC(GPP_B23, NONE), - - /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C1, 0, DEEP), - /* C2 : SMBALERT# ==> GPP_C2_STRAP */ - PAD_NC(GPP_C2, NONE), - /* C3 : SML0CLK ==> EN_UCAM_PWR */ - PAD_CFG_GPO(GPP_C3, 0, DEEP), - /* C4 : SML0DATA ==> EN_UCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_C4, 0, DEEP), - /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ - PAD_NC(GPP_C5, NONE), - /* C6 : SML1CLK ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_C6, 0, DEEP), - /* C7 : SML1DATA ==> USI_INT */ - PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), - - /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG), - /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), - /* D3 : ISH_GP3 ==> WCAM_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), - /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ - PAD_CFG_GPO(GPP_D4, 1, DEEP), - /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ - PAD_CFG_GPO(GPP_D5, 1, DEEP), - /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ - PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG), - /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ - PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), - /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), - /* D13 : ISH_UART0_RXD ==> CAM_PSW_L */ - PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG), - /* D14 : ISH_UART0_TXD ==> SPKR_INT_L */ - PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG), - /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG), - /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG), - /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ - PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), - /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), - /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - - /* E0 : see end of E group */ - /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ - PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG), - /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ - PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), - /* E3 : PROC_GP0 ==> HPS_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), - /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_E4, 0, DEEP), - /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ - PAD_CFG_GPO(GPP_E5, 1, DEEP), - /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ - PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), - /* E7 : PROC_GP1 ==> EN_HPS_PWR */ - PAD_CFG_GPO(GPP_E7, 1, DEEP), - /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ - PAD_CFG_GPO(GPP_E8, 1, DEEP), - /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ - PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), - /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ - PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG), - /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ - PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), - /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ - PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), - /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* E16 : RSVD_TP ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_E16, 1, DEEP), - /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ - PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG), - /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), - /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), - /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), - /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), - /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L - NB. Driven high here so that it is sequenced after WWAN_RST_L; a - PERST# signal would normally be reset by PLRST#, but here it will be - explicitly programmed during a power-down sequence. */ - PAD_CFG_GPO(GPP_E0, 1, DEEP), - - /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ - PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), - /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ - PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), - /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), - /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), - /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ - PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), - /* F7 : GPPF7_STRAP */ - PAD_NC(GPP_F7, NONE), - /* F8 : NC */ - PAD_NC(GPP_F8, NONE), - /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ - PAD_CFG_GPO(GPP_F9, 1, PLTRST), - /* F10 : GPPF10_STRAP */ - PAD_NC(GPP_F10, DN_20K), - /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), - /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), - /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), - /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT), - /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), - /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), - /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */ - PAD_CFG_GPO(GPP_F19, 1, PLTRST), - /* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */ - PAD_CFG_GPO(GPP_F20, 0, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), - /* F22 : NC */ - PAD_NC(GPP_F22, NONE), - /* F23 : NC */ - PAD_NC(GPP_F23, NONE), - - /* H0 : GPPH0_BOOT_STRAP1 */ - PAD_NC(GPP_H0, NONE), - /* H1 : GPPH1_BOOT_STRAP2 */ - PAD_NC(GPP_H1, NONE), - /* H2 : GPPH2_BOOT_STRAP3 */ - PAD_NC(GPP_H2, NONE), - /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG), - /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), - /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC_LOCK(GPP_H13, UP_20K, LOCK_CONFIG), - /* H14 : NC */ - PAD_NC(GPP_H14, NONE), - /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ - PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), - /* H16 : NC */ - PAD_NC(GPP_H16, NONE), - /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* H19 : SRCCLKREQ4# ==> SAR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), - /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), - /* H21 : IMGCLKOUT2 ==> UCAM_MCLK */ - PAD_CFG_GPO(GPP_H21, 0, DEEP), - /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ - PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), - - /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), - /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), - /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - - /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), - /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), - /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), - /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), - /* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), - /* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), - /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), - /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), - - /* GPD0: BATLOW# ==> BATLOW_L */ - PAD_CFG_NF(GPD0, NONE, DEEP, NF1), - /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ - PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), - /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), - /* GPD4: SLP_S3# ==> SLP_S3_L */ - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), - /* GPD5: SLP_S4# ==> SLP_S4_L */ - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), - /* GPD6: SLP_A# ==> SLP_A_L */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7: GPD7_STRAP */ - PAD_NC(GPD7, NONE), - /* GPD8: SUSCLK ==> PCH_SUSCLK */ - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), - /* GPD10: SLP_S5# ==> SLP_S5_L */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), - /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ - PAD_CFG_GPI(GPD11, NONE, DEEP), - - /* Virtual GPIO */ - /* Put unused Cnvi BT UART lines in NC mode since we use USB mode. */ - PAD_NC(GPP_VGPIO_6, NONE), - PAD_NC(GPP_VGPIO_7, NONE), - PAD_NC(GPP_VGPIO_8, NONE), - PAD_NC(GPP_VGPIO_9, NONE), - - /* Put unused Cnvi UART0 lines in NC mode since we use USB mode. */ - PAD_NC(GPP_VGPIO_18, NONE), - PAD_NC(GPP_VGPIO_19, NONE), - PAD_NC(GPP_VGPIO_20, NONE), - PAD_NC(GPP_VGPIO_21, NONE), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L - * To meet timing constrains - drive reset low. - * Deasserted in ramstage. - */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), -}; - -const struct pad_config *__weak variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *__weak variant_gpio_override_table(size_t *num) -{ - *num = 0; - return NULL; -} - -const struct pad_config *__weak variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), -}; - -DECLARE_WEAK_CROS_GPIOS(cros_gpios); - -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h deleted file mode 100644 index ef156f1..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __BASEBOARD_EC_H__ -#define __BASEBOARD_EC_H__ - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) -/* - * EC can wake from S3/S0ix with: - * 1. Lid open - * 2. AC Connect/Disconnect - * 3. Power button - * 4. Key press - * 5. Mode change - * 6. Low battery - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) -#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ - (MAINBOARD_EC_S3_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) -/* - * ACPI related definitions for ASL code. - */ -/* Enable Keyboard Backlight */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT -/* Enable MKBP for buttons and switches */ -#define EC_ENABLE_MKBP_DEVICE -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ - -#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h deleted file mode 100644 index 0de7ffd..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI -/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */ -#define GPE_EC_WAKE GPE0_DW2_17 -/* WP signal to PCH */ -#define GPIO_PCH_WP GPP_E15 -/* EC in RW or RO */ -#define GPIO_EC_IN_RW GPP_F18 -/* Used to gate SoC's SLP_S0# signal */ -#define GPIO_SLP_S0_GATE GPP_F9 -/* GPIO IRQ for tight timestamps / wake support */ -#define EC_SYNC_IRQ GPP_F17_IRQ - -#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/memory.c b/src/mainboard/google/brya/variants/baseboard/skolas/memory.c deleted file mode 100644 index bcad9b4..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/memory.c +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <gpio.h> - -static const struct mb_cfg baseboard_memcfg = { - .type = MEM_TYPE_LP4X, - - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = {40, 30, 30, 30, 30}, - }, - - /* DQ byte map */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, - .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, - }, - .ddr1 = { - .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, - .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, - }, - .ddr2 = { - .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, - .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, - }, - .ddr3 = { - .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, - .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, - }, - .ddr4 = { - .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, - .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, - }, - .ddr5 = { - .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, - .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, - }, - .ddr6 = { - .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, - .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, - }, - .ddr7 = { - .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, - .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, - }, - }, - - /* DQS CPU<>DRAM map */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, - }, - - .ect = 1, /* Enable Early Command Training */ -}; - -const struct mb_cfg *__weak variant_memory_params(void) -{ - return &baseboard_memcfg; -} - -int __weak variant_memory_sku(void) -{ - /* - * Memory configuration board straps - * GPIO_MEM_CONFIG_0 GPP_E11 - * GPIO_MEM_CONFIG_1 GPP_E2 - * GPIO_MEM_CONFIG_2 GPP_E1 - * GPIO_MEM_CONFIG_3 GPP_E12 - */ - gpio_t spd_gpios[] = { - GPP_E11, - GPP_E2, - GPP_E1, - GPP_E12, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} - -bool __weak variant_is_half_populated(void) -{ - /* GPIO_MEM_CH_SEL GPP_E13 */ - return gpio_get(GPP_E13); -} - -void __weak variant_get_spd_info(struct mem_spd *spd_info) -{ - spd_info->topo = MEM_TOPO_MEMORY_DOWN; - spd_info->cbfs_index = variant_memory_sku(); -} diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c b/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c deleted file mode 100644 index 9c2d4aa..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <acpi/acpi_device.h> -#include <baseboard/variants.h> -#include <console/console.h> -#include <device/pci_ops.h> -#include <soc/pci_devs.h> - -#include <drivers/intel/dptf/chip.h> -#include <intelblocks/power_limit.h> - -WEAK_DEV_PTR(dptf_policy); - -void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) -{ - if (!num_entries) - return; - - const struct device *policy_dev = DEV_PTR(dptf_policy); - if (!policy_dev) - return; - - struct drivers_intel_dptf_config *config = policy_dev->chip_info; - - uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); - - u8 tdp = get_cpu_tdp(); - - for (size_t i = 0; i < num_entries; i++) { - if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { - struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; - settings->pl1.min_power = limits[i].pl1_min_power; - settings->pl1.max_power = limits[i].pl1_max_power; - settings->pl2.min_power = limits[i].pl2_min_power; - settings->pl2.max_power = limits[i].pl2_max_power; - soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); - printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", - limits[i].pl1_min_power, - limits[i].pl1_max_power, - limits[i].pl2_min_power, - limits[i].pl2_max_power, - limits[i].pl4_power); - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/73388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Gerrit-Change-Number: 73388 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex: Enable VPU
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72417 ) Change subject: mb/google/rex: Enable VPU ...................................................................... mb/google/rex: Enable VPU BUG=b:270529665 TEST=Verify the build and boot on Rex board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 9a71e95..d328046 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -56,6 +56,7 @@ device domain 0 on device ref igpu on end device ref dtt on end + device ref vpu on end device ref xhci on end device ref shared_sram on end device ref heci1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/72417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Gerrit-Change-Number: 72417 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix: Update phoenix2 VGA BIOS ID
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73372 ) Change subject: soc/amd/phoenix: Update phoenix2 VGA BIOS ID ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/73372/comment/3838efed_9f288089 PS1, Line 247: 1002,15c8 shouldn't this be 1002,1205 to match the pci id in the vbios so that both 1205 and 15c8 cases work as expected? this is at least how it was done on cezanne and i checked there that it was correct -- To view, visit https://review.coreboot.org/c/coreboot/+/73372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie035baf7a0908e1e6382c1810926647bf7182f6c Gerrit-Change-Number: 73372 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 21:26:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation
by Fred Reitberger (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73387 ) Change subject: soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f Gerrit-Change-Number: 73387 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 20:44:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/birman: Add support for 32M flash
by Fred Reitberger (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Zheng Bao, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72963 ) Change subject: mb/amd/birman: Add support for 32M flash ...................................................................... Patch Set 4: (3 comments) Patchset: PS4: Since Birman only has a 32M flash, once building for a 32M flash works, I do not see the need to keep the 16M layouts around. File src/mainboard/amd/birman/board-32M.fmd: https://review.coreboot.org/c/coreboot/+/72963/comment/ada37aa0_e98ce842 PS4, Line 9: AMDFWBODY(CBFS) @2047K The `(CBFS)` should be removed due to updates in CB:72703 The Birman EC binary does not work in the upper 16M region, so go ahead and reserve the entire region for AMDFWBODY. File src/mainboard/amd/birman/chromeos-32M.fmd: https://review.coreboot.org/c/coreboot/+/72963/comment/c2fa8bba_19b21066 PS4, Line 35: AMDFWBODY(CBFS) @2047K Same comment as above -- To view, visit https://review.coreboot.org/c/coreboot/+/72963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0306321f1452e4439a58e3bc5a197a614fce756 Gerrit-Change-Number: 72963 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 20:42:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73387 ) Change subject: soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation ...................................................................... soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation Phoenix' implementation of map_oprom_vendev uses this simplified implementation, so port this back to Cezanne too. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f --- M src/soc/amd/cezanne/graphics.c 1 file changed, 15 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/73387/1 diff --git a/src/soc/amd/cezanne/graphics.c b/src/soc/amd/cezanne/graphics.c index 491ca87..2a06443 100644 --- a/src/soc/amd/cezanne/graphics.c +++ b/src/soc/amd/cezanne/graphics.c @@ -6,14 +6,11 @@ u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev = vendev; - switch (vendev) { case CEZANNE_VBIOS_VID_DID: case BARCELO_VBIOS_VID_DID: - new_vendev = CEZANNE_VBIOS_VID_DID; - break; + return CEZANNE_VBIOS_VID_DID; } - return new_vendev; + return vendev; } -- To view, visit https://review.coreboot.org/c/coreboot/+/73387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f Gerrit-Change-Number: 73387 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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