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Change subject: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
......................................................................
Patch Set 7:
(3 comments)
File src/soc/intel/xeon_sp/uncore_acpi.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169712):
https://review.coreboot.org/c/coreboot/+/71958/comment/ca4aafe5_9db4c2fb
PS7, Line 139: dev = (pds.pds[i].device_handle >> 15 ) & 0x1f;
space prohibited before that close parenthesis ')'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169712):
https://review.coreboot.org/c/coreboot/+/71958/comment/a9bd3e31_fe8fa3dd
PS7, Line 140: func = (pds.pds[i].device_handle >> 12 ) & 0x07;
space prohibited before that close parenthesis ')'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169712):
https://review.coreboot.org/c/coreboot/+/71958/comment/f828ec83_234a2ef9
PS7, Line 527: if (pciexp_find_extended_cap(dev, PCIE_EXT_CAP_ID_ATS, 0)) {
Too many leading tabs - consider code refactoring
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Change subject: soc/intel/xeon_sp/Makefile.inc: Update makefile for spr
......................................................................
soc/intel/xeon_sp/Makefile.inc: Update makefile for spr
Intel SPR-SP chipset has EBG instead of LBG.
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee
---
M src/soc/intel/xeon_sp/Makefile.inc
1 file changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/71959/7
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Change subject: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
......................................................................
soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
Add support for Intel SPR-SP to nb_acpi.c and rename to uncore_acpi.c.
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
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Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/include/soc/acpi.h
D src/soc/intel/xeon_sp/nb_acpi.c
A src/soc/intel/xeon_sp/uncore_acpi.c
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
6 files changed, 673 insertions(+), 455 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/71958/7
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Change subject: mb/google/brya/var/marasov: Turn off camera power during S0ix
......................................................................
Patch Set 10: Code-Review+2
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Change subject: security/tpm/tss/tcg-2.0: Add `tlcl_read_public()`
......................................................................
Patch Set 2:
(2 comments)
File src/security/tpm/tss/tcg-2.0/tss.c:
https://review.coreboot.org/c/coreboot/+/71885/comment/d1b45bb0_f67a4313
PS2, Line 504: /* Unknown handle, returned if the key doesn't exist. */
Is this comment for which switch case?
File src/security/tpm/tss/tcg-2.0/tss_marshaling.c:
https://review.coreboot.org/c/coreboot/+/71885/comment/1a5ca069_577993ef
PS2, Line 550: "%s:%d - "
: "size mismatch: expected %d, remaining %zd\n",
Can fit in one line.
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Change subject: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
......................................................................
Patch Set 11:
(4 comments)
File src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/71945/comment/5e3bbfdd_ffed6f19
PS8, Line 88: #define SPI0_IO_2 45
: #define SPI0_IO_3 46
: #define SPI0_MOSI_IO_0 47
: #define SPI0_MOSI_IO_1 48
: #define SPI0_TPM_CSB 49
: #define SPI0_FLASH_0_CSB 50
: #define SPI0_FLASH_2_CSB 51
: #define SPI0_CLK 52
> Tim, could you check this?
These fields are not defined in EDS, but I can find them while using Cscript. I remove these fields but keep the order here. Also add comment here to explain the reason why the order is kept.
https://review.coreboot.org/c/coreboot/+/71945/comment/c6e7f993_0d6ef270
PS8, Line 187: #define GPP_E20 132
: #define GPP_E21 133
: #define GPP_E22 134
: #define GPP_E23 135
> Tim, could you check this?
These fields are not defined in EDS but can be found while using Cscript. I keep them here to make the order correct. These fields are also mentioned in EDS 13.9.1. Is it necessary to remove them?
https://review.coreboot.org/c/coreboot/+/71945/comment/8a2b3d26_5488aa27
PS8, Line 192: GPP_E23
> GPP_E19
Although GPP_E23 is not defined in EDS but it does exist, should we change this to GPP_E19?
File src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/71945/comment/61319960_d5aa37f9
PS6, Line 374: #define GPIO_DRIVER_IRQ_ROUTE_MASK 8
: #define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0
: #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8
> Tim, could you check this?
I removed these definitions.
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Change subject: soc/intel/xeon_sp: add Kconfig file for SPR-SP
......................................................................
Patch Set 7: Code-Review+1
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Change subject: soc/amd: Create AMD common reset code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/reset.h:
https://review.coreboot.org/c/coreboot/+/72658/comment/ee81f144_07886318
PS1, Line 10: #include <soc/southbridge.h>
:
:
: void do_warm_reset(void);
maybe just one empty line?
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Change subject: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
......................................................................
soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset.
These changes are in accordance with the documentation:
* Intel(R) Emmitsburg Platform Controller Hub External Design
Specification. Document Number: 606161
* Emmitsburg PCH BIOS Specification. Document Number: 631063.
Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com>
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87
---
A src/soc/intel/xeon_sp/ebg/Makefile.inc
A src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h
A src/soc/intel/xeon_sp/ebg/include/soc/pcr_ids.h
A src/soc/intel/xeon_sp/ebg/include/soc/pmc.h
A src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h
A src/soc/intel/xeon_sp/ebg/lockdown.c
A src/soc/intel/xeon_sp/ebg/soc_gpio.c
A src/soc/intel/xeon_sp/ebg/soc_pch.c
A src/soc/intel/xeon_sp/ebg/soc_pmutil.c
9 files changed, 868 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/71945/11
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72660 )
Change subject: src/sbom/Makefile.inc: Fix variable expansion
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> would you please rebase on https://review.coreboot. […]
Please rebase on #70251.
"SBOM" patches still creating a "go" directory into home directory (/home/current_user/go).
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