coreboot-gerrit February 2023

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[M] Change in coreboot[master]: soc/intel/common: Add Intel Trace Hub driver
by Subrata Banik (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla, Pratikkumar V Prajapati. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72722 ) Change subject: soc/intel/common: Add Intel Trace Hub driver ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: wondering why don't we read the BAR of Intel TH instead reading the FSP HOB for a PCI device ? -- To view, visit https://review.coreboot.org/c/coreboot/+/72722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Gerrit-Change-Number: 72722 Gerrit-PatchSet: 3 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 10:13:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Update soc_intel_meteorlake_config structure
by Subrata Banik (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72871 ) Change subject: soc/intel/meteorlake: Update soc_intel_meteorlake_config structure ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5 Gerrit-Change-Number: 72871 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 10:11:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Modify variant specific devicetree
by build bot (Jenkins) (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72872 ) Change subject: mb/google/brya/var/omnigul: Modify variant specific devicetree ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/omnigul/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-170055): https://review.coreboot.org/c/coreboot/+/72872/comment/89711a3f_43b8b146 PS1, Line 12: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/72872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67 Gerrit-Change-Number: 72872 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 10:07:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Modify variant specific devicetree
by Jamie Chen (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli. Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72872 ) Change subject: mb/google/brya/var/omnigul: Modify variant specific devicetree ...................................................................... mb/google/brya/var/omnigul: Modify variant specific devicetree add SoC config and .early_init = 1 in I2C1 BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67 Signed-off-by: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/72872/1 diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index d243668..84fe0bb 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -9,6 +9,34 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | TouchScreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/72872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67 Gerrit-Change-Number: 72872 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Modify NVMe and UFS Storage support
by Jamie Chen (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Marx Wang, Subrata Banik, Jamie Chen, Tarun Tuli, Kyle Lin. Hello build bot (Jenkins), Subrata Banik, Tarun Tuli, Ian Feng, Subrata Banik, Dtrain Hsu, Kyle Lin, Marx Wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72090 to look at the new patch set (#8). Change subject: mb/google/brya/var/omnigul: Modify NVMe and UFS Storage support ...................................................................... mb/google/brya/var/omnigul: Modify NVMe and UFS Storage support 1. Add fw_config:STORAGE_UFS & STORAGE_NVME to switch storage. 2. rp11 off change to on. BUG:b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b Signed-off-by: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/overridetree.cb 1 file changed, 39 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/72090/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/72090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b Gerrit-Change-Number: 72090 Gerrit-PatchSet: 8 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
by Simon Chou (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: TimLiu-SMCI, Jonathan Zhang, Ryback Hung, David Hendricks, Paul Menzel, Angel Pons, Tim Chu. Simon Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71953 ) Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/71953/comment/c875be46_8eccdd40 PS6, Line 467: pci_write_config32(dev, SPI_BIOS_DECODE_EN, bde); > Sorry, looking back at this I think what Paul meant is: […] Update it according to the review comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/71953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3366817b42a5878f16575698ebc546fa7852e285 Gerrit-Change-Number: 71953 Gerrit-PatchSet: 9 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 10:01:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Chou <simonchou(a)supermicro.com.tw> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/{common, meteorlake}: Add support for new MCH
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72835 ) Change subject: soc/intel/{common, meteorlake}: Add support for new MCH ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/72835/comment/33654ec4_ca7665cd PS1, Line 184: case PCI_DID_INTEL_MTL_P_ID_5: : soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_5]; > this is dead code at this moment as we are not overriding anything per SKU. […] Right, I will remove the code now, and can be added later if the SKU has specific power limits. -- To view, visit https://review.coreboot.org/c/coreboot/+/72835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 Gerrit-Change-Number: 72835 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 09:43:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Update soc_intel_meteorlake_config structure
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72871 ) Change subject: soc/intel/meteorlake: Update soc_intel_meteorlake_config structure ...................................................................... soc/intel/meteorlake: Update soc_intel_meteorlake_config structure The patch removes hybrid_storage_mode variable from soc_intel_meteorlake_config struct since hybrid storage is no longer supported on Meteor Lake platform. TEST=Verify the build for Rex board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5 --- M src/soc/intel/meteorlake/chip.h 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/72871/1 diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 4e95321..1b9d192 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -300,11 +300,6 @@ /* Enable(1)/Disable(0) HPD/DDC */ uint8_t ddi_ports_config[DDI_PORT_COUNT]; - /* Hybrid storage mode enable (1) / disable (0) - * This mode makes FSP detect Optane and NVME and set PCIe lane mode - * accordingly */ - uint8_t hybrid_storage_mode; - /* * Override CPU flex ratio value: * CPU ratio value controls the maximum processor non-turbo ratio. -- To view, visit https://review.coreboot.org/c/coreboot/+/72871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5 Gerrit-Change-Number: 72871 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s
by Jan Samek (Code Review) 07 Feb '23

07 Feb '23

Jan Samek has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72804 ) Change subject: mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s ...................................................................... mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. BUG=none TEST=Test link stability using a panel with minimum re-power delay of 1 s. Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c 1 file changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/72804/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c index 7b16254..c57d598 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c @@ -82,8 +82,8 @@ cfg->t2_delay = 0x01; /* LVDS to backlight active delay: 200 ms */ cfg->t3_timing = 0x04; - /* Minimum re-power delay: 500 ms */ - cfg->t12_timing = 0x0a; + /* Minimum re-power delay: 1 s */ + cfg->t12_timing = 0x14; /* Backlight off to LVDS inactive delay: 200 ms */ cfg->t4_timing = 0x04; /* Enable LVDS to VDD inactive delay. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b Gerrit-Change-Number: 72804 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/geralt: Init MT6359P only once in ramstage
by Liju-Clr Chen (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Yidi Lin, Yu-Ping Wu. Liju-Clr Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72839 ) Change subject: mb/google/geralt: Init MT6359P only once in ramstage ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72839/comment/3d20a00f_b04ac2ff PS1, Line 12: > add this to commit message. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/72839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd Gerrit-Change-Number: 72839 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 09:06:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2023