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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71593 )
Change subject: src: Add and use POST_BOOTBLOCK_C_ENTRY
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
I'd let <console/console.h> chain-include <commonlib/console/post_codes.h>.
Please let me know your thoughts.
File src/soc/intel/skylake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/71593/comment/4cdea502_ae1500b9
PS2, Line 4: <commonlib/console/post_codes.h>
<console/console.h> is needed for post_code() function
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Hello Tarun Tuli, Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72835
to look at the new patch set (#2).
Change subject: soc/intel/{common, meteorlake}: Add support for new MCH
......................................................................
soc/intel/{common, meteorlake}: Add support for new MCH
The patch adds support for new Meteor Lake MCH (ID:0x7d16).
TEST=Build and boot the system having MCH ID:0x7d16.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/meteorlake/bootblock/report_platform.c
3 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/72835/2
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Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
......................................................................
Patch Set 8: Code-Review+2
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Change subject: sc7280/boot,shrm: Update qclib blobs binaries from 35 to 43
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/qc_blobs/+/70743/comment/55088975_cfa5f2f1
PS1, Line 7: shrm
> maybe something like "sc7280/boot,shrm:" would make it more clear?
Updated related commit message, can you please review
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Change subject: soc/intel: Use common codeflow for MP init
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> CPU frequency seems to be dropping with the changes. On ToT bin it was ~1200MHz but it drops to ~400MHz for few cases with changes for rex.
>
> Steps to reproduce:
> 1. Check CPU information from AP console.
> 2. Compare all occurrence of key word "CPU MHz"
> ```
> localhost ~ cat /proc/cpuinfo
> ```
>
That's really strange as the bootflow is pretty much identical. No new code is run.
Are you sure CPU freq change is not to be expected? You can see what power states are expected with powertop. cpuinfo just shows the current cpu freq which depends on the load.
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Change subject: soc/amd/picasso/soc_util: use cpuid_match
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/picasso/soc_util.c:
https://review.coreboot.org/c/coreboot/+/72860/comment/0cd599b5_2741cc9d
PS4, Line 97: 0xffffff00
> CPUID_ALL_STEPPINGS_AND_BASE_MODELS_MASK? Don't know how to shorter this.
sounds good to me and i also can't think of a shorter name that still makes it clear enough what it;s doing. update the patch
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Change subject: soc/intel/alderlake: Remove unused S0IX variable
......................................................................
Patch Set 2: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72860
to look at the new patch set (#5).
Change subject: soc/amd/picasso/soc_util: use cpuid_match
......................................................................
soc/amd/picasso/soc_util: use cpuid_match
Now that there is a cpuid_match function, we can use it instead of doing
basically the same thing manually. In the functions is_fam17_1x and
is_fam17_2x both the stepping number and the lower nibble of the model
number are masked out. To avoid having magic constants in the code,
introduce the CPUID_ALL_STEPPINGS_AND_BASE_MODELS_MASK definition.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I758f9564c08c62c747cc4f93a8d6b540a1834a62
---
M src/arch/x86/include/arch/cpu.h
M src/soc/amd/picasso/soc_util.c
2 files changed, 26 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/72860/5
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Change subject: soc/intel/rtd3: Hook up supported states to Kconfig
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72765/comment/7353c843_f4c2467d
PS1, Line 9: S3 does not support D3Cold,
> Adjusted so it's configurable, but defaults as there are 3 boards in the tree that need it.
Done
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